Methods for precise definition of integrated circuit chip edges

• US 5,925,924 A
• Filed: 04/14/1997
• Issued: 07/20/1999
• Est. Priority Date: 07/26/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Marmillion, Patricia Ellen, Cronin, John Edward, Pierson, Bernadette Ann, Howell, Wayne John, Schmidt, Dennis Arthur, Kalter, Howard Leo, Palagonia, Anthony
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/843,177
• Time in Patent Office: 827 Days
• Field of Search: 257/622, 257/620, 257/686, 257/723
• US Class Current: 257/622
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Claims

1. A wafer segment comprising:

a planar group of at least one IC chip, each IC chip including integrated circuitry, said planar group having a plurality of edge surfaces, at least one edge surface of said plurality of edge surfaces being spaced within a photolithographic tolerance from integrated circuitry of said at least one IC chip; and

an insulating layer disposed on said at least one edge surface of said plurality of edge surfaces, said spacing within a photolithographic tolerance and said insulating layer facilitating stacking of said wafer segment into an electronic module, wherein said at least one edge surface forms a part of a side surface of said electronic module when said wafer segment is stacked as part of said electronic module.

2. The wafer segment of claim 1, wherein said planar grouping comprises a single IC chip.

3. The wafer segment of claim 1, wherein said planar grouping comprises a planar array of IC chips.

4. A wafer segment comprising:

a planar group of at least one IC chip, each IC chip including integrating circuitry, said planar group having a plurality of edge surfaces; and

at least one edge surface of said plurality of edge surfaces being spaced within a photolithographic tolerance from integrated circuitry of said at least one IC chip, said spacing within said photolithographic tolerance facilitating stacking of said wafer segment into an electronic module, wherein said at least one edge surface forms a part of a side surface of said electronic module when said wafer segment is stacked as part of said electronic module.