Low cost and highly reliable chip-sized package

• US 5,925,934 A
• Filed: 01/04/1996
• Issued: 07/20/1999
• Est. Priority Date: 10/28/1995
• Status: Expired due to Fees

• Current Assignee: Institute of Microelectronics
• Original Assignee: Institute of Microelectronics
• Inventors: Lim, Thiam Beng
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/582,744
• Time in Patent Office: 1,293 Days
• Field of Search: 257/787, 257/734, 257/735, 257/737, 257/738, 257/707, 257/693, 257/686, 257/778, 257/723, 257/490, 257/678, 257/670, 257/673, 174/52.4, 228/180.22, 228/179.1, 228/180.1, 228/180.2
• US Class Current: 257/778
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83104 by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports. Alternatively, prior to encapsulation, the chip ports are positioned to sit on a mold, so that removing the mold leaves exposed the portions of the chip ports that were in contact with the mold. The mold may have an array of mold bumps or mold pockets upon which the chip ports sit. Removing the mold, exposes portions of the chip ports and leaves an array of openings in the encapsulant. Another method to form the array of openings in the encapsulant and expose portions of the chip ports uses an array of pins that are inserted in the encapsulant before it cures. The pins are inserted to contact the chip ports. Retracting the array of pins forms the array of openings in the encapsulant and exposes portions of the chip ports that were in contact with the pins.

Claims

1. A chip-sized package comprising:

a chip having an active surface;

chip ports arranged in an array on said active surface;

an encapsulant which encapsulates said chip and portions of said chip ports located nearest said active surface, portions of said chip ports which are located away from said active surface being exposed from said encapsulant;

a package port attached to the exposed portions of each chip port, wherein each package port is electrically connectable to a circuit board;

at least two frame tie-bars positioned opposite each other and not extending entirely across a surface of the chip; and

a die attach which attaches the chip to the at least two frame tie-bars.

2. The chip-sized package of claim 1, wherein said frame tie-bar and said array chip ports are on opposite surfaces of said chip.

3. The chip-sized package of claim 1, wherein said encapsulant is an epoxy molding compound.

4. The chip-sized package of claim 1, wherein said array of chip ports comprises an array of conductive bumps or balls.

5. The chip-sized package of claim 1, wherein said array of chip ports comprises an array of metal bumps.

6. The chip-sized package of claim 1, wherein said array of chip ports comprises an array of conductive polymer bumps or balls.

7. The chip-sized package of claim 1, wherein said array of chip ports is an array of solder bumps.

8. The chip-sized package of claim 1, wherein said array of package ports is an array of conductive polymer bumps or balls.

9. The chip-sized package of claim 1, wherein said array of package ports is an array of solder bumps or balls.

10. The chip-sized package of claim 1, wherein the frame tie-bars are connected to an inactive surface of the chip.