Display apparatus capable of image display for video signals of plural kinds

• US 5,926,174 A
• Filed: 05/23/1996
• Issued: 07/20/1999
• Est. Priority Date: 05/29/1995
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Shibamiya, Yoshikazu, Suga, Kazumi
• Primary Examiner(s): Zimmerman, Mark K.
• Assistant Examiner(s): Laneau, Ronald
• Application Number:
  US08/652,153
• Time in Patent Office: 1,153 Days
• Field of Search: 345/213, 345/115, 348/516, 348/497, 348/536
• US Class Current: 345/213
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2320/08 Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2340/0442 Handling or displaying different aspect ratios, or changing the aspect ratio
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H04N 17/04 for receivers
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/445 for displaying additional information H04N5/50 takes precedence
• CPC Class Codes: H04N 5/57 Control of contrast or brightness
• CPC Class Codes: H04N 5/66 Transforming electric information into light information scanning details H04N3/00
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 Multi-standard receivers

Abstract

In an apparatus for displaying the image of an input video signal, utilizing a clock signal which is phase synchronized with the input video signal, change in the state of the input video signal is made easily detectable. For this purpose there is disclosed a display apparatus provided with a clock generating circuit including a PLL circuit and adapted to generate a clock signal which is phase synchronized with the input video signal, and a display circuit for displaying the image relating to the input video signal utilizing the clock signal generated by the clock generating circuit. A detection circuit detects the state of the input video signal according to whether the PLL circuit is in the locked state.

Claims

1. A display apparatus for displaying an image of an input image signal, utilizing a clock signal which is phase synchronized with said input image signal, comprising:

clock generating means including a phase comparator for comparing the phase of the synchronization signal in said input image signal with that of said clock signal and adapted for generating a clock signal which is phase synchronized with said input image signal;

display means for displaying the image represented by said input image signal, utilizing the clock signal generated by said clock generating means, with said display means having a plurality of display modes;

detection means for detecting the display mode of said display means corresponding to a state of said input image signal; and

control means for controlling the comparing operation of said phase comparator according to the display mode detected by said detection means.

2. An apparatus according to claim 1, wherein said display means includes a sampling circuit for sampling said input image signal according to said clock signal, and a display circuit for displaying the image relating to said sampled image signal.

3. An apparatus according to claim 1, wherein said control means is adapted to control the timing of the phase comparing operation of said phase comparator, according to the output of said detection means.

4. An apparatus according to claim 1, wherein said control means is adapted to change the state of the synchronization signal entered into said phase comparator, according to the output of said detection means.

5. An apparatus according to claim 1, wherein said synchronization signal is composed of a rectangular wave.

6. An apparatus according to claim 1, wherein said phase comparator is capable of effecting said comparing operation at the timing of upshift and downshift of said synchronization signal, and said control means is adapted to control the timing of said comparing operation according to the output of said detection means.

7. An apparatus according to claim 1, wherein said control means includes a polarity inverting circuit for inverting the polarity of said synchronization signal, and said polarity inverting circuit is adapted to control the polarity of said synchronization signal according to the output of said detection means.

8. An apparatus according to claim 1, further comprising input means for entering image signals of plural kinds, mutually different in the state of the synchronization signal.

9. An apparatus according to claim 1, wherein said control means includes a memory for storing mode data, indicating the states of the synchronization signal of the image signals of plural kinds, and is adapted to compare the result of detection of said detection means with the states of the image signals of plural kinds indicated by said mode data and to control the comparing operation of said phase comparator based on the result of said comparison.

10. An apparatus according to claim 1, wherein said display means includes a ferroelectric liquid crystal display.

34. An apparatus according to claim 1, wherein said plurality of display modes have different solutions.

11. A display apparatus for displaying an image of an input image signal, utilizing a clock signal which is phase synchronized with said input image signal, comprising:

clock generating means including a PLL circuit and adapted for generating a clock signal which is phase synchronized with said input image signal, said clock generating means generating a control signal indicating whether said PLL circuit is in a locked state;

display means for displaying the image represented by said input image signal, utilizing said clock signal generated by said clock generating means, with said display means having a plurality of display modes; and

detection means for detecting the display mode of said display means corresponding to a state of said input image signal according to the control signal generated by said clock generating means.

12. An apparatus according to claim 11, further comprising control means for controlling the generating operation of said clock generating means according to the output of said detection means.

13. An apparatus according to claim 12, further comprising input means for entering image signals of plural kinds mutually different in the state of the synchronization signal, wherein said detection means is adapted to detect whether the synchronization signal in said input image signal has changed, according to said locked state signal.

14. An apparatus according to claim 13, wherein said control means is adapted to discriminate the kind of the synchronization signal in said input image signal and to set the operating parameters of said clock generating means according to the kind of said synchronization signal.

15. An apparatus according to claim 12, wherein said control means is adapted to control the phase comparing operation of said PLL circuit according to said locked state signal.

16. An apparatus according to claim 12, wherein said control means is adapted to control the timing of the phase comparing operation of said PLL circuit according to said locked state signal.

17. An apparatus according to claim 12, wherein said control means is adapted to change the state of the synchronization signal entered into said PLL circuit, according to said locked state signal.

18. An apparatus according to claim 11, wherein said display means includes a sampling circuit for sampling said input image signal according to said clock signal, and a display circuit for displaying the image relating to said sampled image signal.

19. An apparatus according to claim 11, further comprising input means for entering image signals of plural kinds mutually different in the state of the synchronization signal, wherein said detection means is adapted to detect the kind of said input image signal according to the control signal released by said clock generating means.

35. An apparatus according to claim 11, wherein said plurality of display modes have different solutions.

20. A display apparatus for displaying an image of an input image signal, utilizing a clock signal which is phase synchronized with said input image signal, comprising:

clock generating means including a PLL circuit and adapted for generating a clock signal which is phase synchronized with said input image signal, said clock generating means generating a control signal indicating whether said PLL circuit is in a locked state, with said clock generating means having a plurality of operation modes;

display means for displaying the image represented by said input image signal, utilizing said clock signal generated by said clock generating means, with said display means having a plurality of display modes;

detection means for detecting the display mode of said display means corresponding to a state of said input image signal; and

mode setting means for setting the operating mode of said clock generating means according to the control signal generated by said clock generating means and the display mode detected by said detection means.

21. An apparatus according to claim 20, wherein said mode setting means is adapted to set the operating parameters of said PLL circuit according to said control signal and the output of said detection means.

22. An apparatus according to claim 21, wherein said mode setting means is adapted to set the operating parameters of said PLL circuit so as to generate a clock signal matching the state of said input image signal detected by said detection means.

36. An apparatus according to claim 20, wherein said plurality of display modes have different solutions.

23. A signal processing apparatus comprising:

input means for entering a video signal containing vertical synchronization signals and horizontal synchronization signals, with horizontal synchronization periods of said horizontal synchronization signals varying within one vertical synchronization period;

synchronization signal detecting means for detecting, utilizing said input video signal, the horizontal synchronization periods of said input video signals and the timing of change of the horizontal synchronization periods in one vertical synchronization period;

clock generating means for generating a clock signal which is phase synchronized with said horizontal synchronization signals; and

control means for controlling a generating operation of said clock generating means according to a detection result of said synchronization signal detecting means.

24. An apparatus according to claim 23, further comprising display means for displaying the image relating to said input video signal utilizing said clock signal.

25. A display control apparatus for controlling a display device, comprising:

input means for inputting an image signal;

mode setting means for detecting a state of said input image signal and for setting a display mode of the display device between a plurality of display modes according to the detection result;

clock generating means for generating a clock signal which is phase synchronized with said input image signal;

control means for controlling a clock generating operation of said clock generating means according to the display mode set by said mode setting means;

processing means for processing said input image signal according to the clock signal and supplying the processed image signal to said display device, said display device displaying an image represented by said image signal supplied from said processing means.

26. An apparatus according to claim 25, wherein said plurality of display modes have different solutions.

27. An apparatus according to claim 25, wherein said processing means comprises converting means for sampling the input image signal according to the clock signal and converting the sampled image signal into a digital image signal.

28. An apparatus according to claim 25, wherein said processing means comprises interpolation means for interpolating the input image signal according to the display mode set by said mode setting means.

29. A display control apparatus for controlling a display device, comprising:

detection means for detecting a state of an input video signal;

mode setting means for setting a display mode of said display device between n different display modes corresponding to different states of the input video signal on the basis of the detection results of said detection means,

said mode setting means setting the display mode of said display device to be a predetermined display mode when the state of the input video signal detected by said detection means corresponds to a display mode other than the n different display modes; and

processing means for processing the input video signal according to the display mode set by said mode setting means and for supplying the processed video signal to the display device, the display device displaying an image represented by the video signal supplied from said processing means.

30. An apparatus according to claim 29, wherein said mode setting means comprises storing means for storing n different states of the input video signal corresponding to the n different display modes.

31. An apparatus according to claim 29, wherein the n different display modes have different solutions.

32. An apparatus according to claim 29, wherein said processing means comprises clock generating means for generating a clock signal phase synchronized with the input video signal, said clock generating means generating the clock signal according to the display mode set by said mode setting means.

33. An apparatus according to claim 29, wherein said processing means comprises interpolation means for interpolating the input video signal according to the display mode set by said mode setting means.