Method and apparatus for regulating the voltage supplied to an integrated circuit

• US 5,926,394 A
• Filed: 09/30/1996
• Issued: 07/20/1999
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nguyen, Don J., Noble, James L.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/724,173
• Time in Patent Office: 1,023 Days
• Field of Search: 364/488, 364/489, 364/490, 323/271, 323/280, 327/112, 327/250, 327/264
• US Class Current: 323/271
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A method and apparatus for regulating a voltage supplied by a power supply to an integrated circuit. A signal is sent to the power supply. This signal signifies that a change in the current drawn by the integrated circuit from the power supply will occur. Next, the voltage supplied by the power supply to the integrated circuit is adjusted in response to this signal before the change in current occurs. The adjustment is in a direction that will compensate for the anticipated voltage transient that will result from the change in the current.

Claims

1. A method for regulating a voltage supplied by a power supply to an integrated circuit comprising:

sending a first signal to the power supply to signify that current drawn by the integrated circuit from the power supply will increase;

raising the voltage supplied by the power supply to the integrated circuit, in response to the first signal, before the current increases, to compensate for an anticipated voltage transient;

sending a second signal to the power supply to signify that current drawn by the integrated circuit from the power supply will decrease; and

lowering the voltage supplied by the power supply to the integrated circuit, in response to the second signal, before the current decreases, to compensate for an anticipated voltage transient.

2. The method of claim 1, wherein the steps of sending a signal and raising and lowing the voltage occur in a mobile computer system.

3. The method of claim 1, wherein the integrated circuit is a processor and the current increases and decreases when the processor switches between a sleep mode and wake mode.

4. The method of claim 1, wherein the first and second signals are sent from the integrated circuit.

5. The method of claim 1, wherein the first and second signals are sent from a subsystem within a computer system.

6. A method for regulating a voltage supplied by a power supply to a processor within a computer system comprising:

sending a first signal to the power supply to signify that the processor will switch from a sleep mode to a wake mode;

raising the voltage supplied by the power supply to the processor, in response to the first signal, before the processor switches from the sleep mode to the wake mode, to compensate for an anticipated voltage transient

sending a second signal to the power supply to signify that the processor will switch from a wake mode to a sleep mode; and

lowering the voltage supplied by the power supply to the processor, in response to the second signal, before the processor switches from the wake mode to the sleep mode, to compensate for an anticipated voltage transient.

7. The method of claim 6, wherein the first and second signals are sent from the processor.

8. The method of claim 6, wherein the first and second signals are received by the processor and cause the processor to subsequently switch between the sleep mode and the wake mode.

9. The method of claim 6, wherein switching from the sleep mode to the wake mode results in an increase in a current drawn by the processor from the power supply.

10. A computer system comprising:

a processor to switch between a sleep mode and a wake mode in response to a first signal;

a transistor having a gate and a source/drain region, the gate to receive the first or a second signal; and

a power supply coupled to the source/drain region, of the transistor and supplying a supply voltage to the processor, the power supply to adjust the supply voltage by raising the supply voltage before the processor switches from the sleep mode to the wake mode, and lowering the supply voltage before the processor switches from the wake mode to the sleep mode in response to the first or second signal.

11. The computer system of claim 10 further comprising a resistor in series with the transistor configured to lower an input voltage to the power supply when the transistor is turned on, thereby causing the power supply to raise the supply voltage.

12. The computer system of claim 11, wherein the transistor is an n-channel transistor.

13. The computer system of claim 10, wherein the gate of the transistor receives the first signal and the power supply adjusts the supply voltage responsive to the first signal.

14. The computer system of claim 10, wherein the gate of the transistor receives the second signal generated by the processor in response to the processor receiving the first signal, and the power supply adjusts the supply voltage responsive to the second signal.