Logic synthesis method, semiconductor integrated circuit and arithmetic circuit

• US 5,926,396 A
• Filed: 05/24/1996
• Issued: 07/20/1999
• Est. Priority Date: 05/26/1995
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ohara, Kazutake
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/653,651
• Time in Patent Office: 1,152 Days
• Field of Search: 364/488-491, 364/578, 364/438, 364/113, 364/345, 364/190, 326/41, 326/80, 365/189, 307/475, 257/299
• US Class Current: 326/80
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 7/5312 using carry save adders

Abstract

A top-down design technique is used to design a semiconductor integrated circuit having a plurality of registers and a plurality of combinational circuits each of which is connected between the registers. When a semiconductor integrated circuit is logic-synthesized from a register transistor level, a front section of a critical path-containing combinational circuit is driven by a high voltage from a high-voltage source while the remaining section and other combinational circuits with no critical path are driven by a low voltage from a low-voltage source. A level shifter is placed at the stage before the critical path-containing combinational circuit. The level shifter converts a low-voltage signal into a high-voltage one. This invention facilitates logic synthesis of a low-power semiconductor circuit without increasing the maximum signal propagation delay of the critical path and without having to provide a level shifter in a combinational circuit.

Claims

1. A method for designing a semiconductor integrated circuit having a plurality of combinational circuits each of which includes a signal propagation path and having registers which are provided at stages respectively preceding and succeeding at least one of said plurality of combinational circuits, said method comprising:

a first step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay not more than a design delay upper limit, said combinational circuit into a combinational circuit of a first type driven by a low voltage from a low-voltage source, and mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay above the design delay upper limit, said combinational circuit into a combinational circuit of a second type of which part is driven by a high voltage from a high-voltage source and of which remaining part is driven by a low voltage from said low-voltage source in order that the signal propagation path of said combinational circuit has a signal propagation delay below the design delay upper limit; and

a second step of remapping, when there is found as a result of checking, a mixture in which an output from said remaining part of said second-type combinational circuit that is driven by a low voltage from said low-voltage source is input to a part of another second-type combinational circuit that is driven by a high voltage from said high-voltage source, said remaining part of said second-type combinational circuit that is driven by a low voltage from said low-voltage source so as to be driven by a high voltage from said high-voltage source.

2. A method for designing a semiconductor integrated circuit according to claim 1, wherein, in said first step, said part of said second-type combinational circuit is a front section of said second-type combinational circuit and said remaining part of said second-type combinational circuit is a rear section of said second-type combinational circuit.

3. A method for designing a semiconductor integrated circuit according to claim 2,

said first step including:

initially mapping all of said plural combinational circuits into respective combinational circuits of the first type;

determining whether there exists a first-type combinational circuit in said first-type combinational circuits of which signal propagation path has a signal propagation delay above the design delay upper limit, and if such a first-type combinational circuit is found to exist, remapping said first-type combinational circuit into a combinational circuit of the second type.

4. A method for designing a semiconductor integrated circuit according to claim 2 or claim 3, said first step including:

conceptually dividing, if there exists a combinational circuit of the first type that has a signal propagation delay above the design delay upper limit, said first-type combinational circuit into plural combinational circuit elements, and remapping the first of said plural combinational circuit elements into a combinational circuit of the second type so as to form a first remapped combinational circuit;

checking if said first remapped combinational circuit has a signal propagation delay above the design delay upper limit; and

remapping, when said first remapped combinational circuit is found to still have a signal propagation delay above the design delay upper limit, the second combinational circuit element, located next to the aforesaid first combinational circuit element in the direction of signal propagation in said first-type combinational circuit, into a combinational circuit of the second type so as to form a second remapped combinational circuit, checking if said second remapped combinational circuit has a signal propagation delay above the design delay upper limit, and repeating said remapping/checking processing.

5. A method for designing a semiconductor integrated circuit according to claim 2 or claim 3,

said first step including:

conceptually dividing, when a front section of a combinational circuit of the first type is remapped into a combinational circuit of the second type, said first-type combinational circuit into plural combinational circuit elements; and

repeating a binary search for finding a combinational circuit element in said plural combinational circuit elements which becomes said front section until said first-type combinational circuit has a signal propagation delay below the design delay upper limit and the number of combinational circuits of the second type is minimized.

6. A method for designing a semiconductor integrated circuit according to claim 2,

said first step including:

estimating, by making use of a combinational circuit of the first type and a register driven by a low voltage from said low-voltage source, a sum of signal propagation delays of said first-type combinational circuit and said register;

checking if said sum exceeds the design delay upper limit;

mapping, if said sum is found to be below the design delay upper limit, said first-type combinational circuit into a combinational circuit of the first type; and

mapping, if said sum is found to be above the design delay upper limit, a front section of said first-type combinational circuit into a combinational circuit of the second type.

7. A method for designing a semiconductor integrated circuit according to claim 6,

said first step including:

conceptually dividing, when a result of said signal propagation estimation operation shows that there exists a combinational circuit of the first type that has a signal propagation delay above the design delay upper limit, said first-type combinational circuit into plural combinational circuit elements, and calculating, based on the ratio of the signal propagation delay estimation result and the design delay upper limit, a ratio of the number of combinational circuit elements to be mapped into combinational circuits of the second type and the number of combinational circuit elements to be mapped into combinational circuits of the first type;

calculating, based on said number of combinational circuit elements forming said first-type combinational circuit and said calculated ratio, a range of a front section to be mapped into a combinational circuit of the second type; and

mapping a combinational circuit element of said plural combinational circuit elements that falls in said calculated range into a combinational circuit of the second type, and mapping the remaining combinational circuit elements into combinational circuits of the first type.

8. A method for designing a semiconductor integrated circuit according to claim 1 further comprising, before said first step, the steps of:

designating a part of a combinational circuit to be mapped into a combinational circuit of the second type;

mapping said part into a combinational circuit of the second type; and

placing a level shifter at a stage before said second-type combinational circuit, said level shifter being driven by a high voltage from said high-voltage source.

9. A method for designing a semiconductor integrated circuit according to claim 8 wherein said designated part of said combinational circuit is a rear section thereof.

10. A method for designing a semiconductor integrated circuit according to claim 8 or claim 9 wherein said designation is made by a functional description including a description that designates said part to be mapped into a combinational circuit of the second type and said functional description is inputted prior to said first step.

11. A method for designing a semiconductor integrated circuit according to claim 8 or claim 9 further comprising, after said second step, the step of:

removing a level shifter that is determined to lie between combinational circuits of the second type.

12. A method for designing a semiconductor integrated circuit according to claim 1,

said first step including:

(i) setting in a combinational circuit of combinational circuit elements that has a signal propagation delay above the design delay upper limit a plurality of windows having a specified size, each said window serving as a search range;

(ii) selecting from among said plural windows a window that contains a group of combinational circuit elements of said elements whose total area or total delay is the smallest, and mapping said group as a part of said combinational circuit into a combinational circuit of the second type; and

(iii) placing a level shifter at a stage before said mapped second-type combinational circuit.

13. A method for designing a semiconductor integrated circuit according to claim 12 wherein said window size is calculated based on said signal propagation delay and said design delay upper limit.

14. A method for designing a semiconductor integrated circuit according to claim 12 further comprising, after said second step, the step of:

removing a level shifter that is determined to lie between combinational circuits of the second type.

15. A method for designing a semiconductor integrated circuit according to claim 1 or claim 2,

said second step including:

checking if said remapping from first type into second type produces a new mixture of a combinational circuit of the first type and a combinational circuit of the second type arranged such that an output from said first-type combinational circuit serves as an input to said second-type combinational circuit;

when such a new mixture is found to exist, remapping said first-type combinational circuit into a combinational circuit of the second type; and

repeating said checking/remapping processing.

16. A method for designing a semiconductor integrated circuit according to claim 1 wherein:

register-transfer-level design data is inputted which describes a plurality of registers and a plurality of combinational circuits each of which is connected between said registers; and

said logic cell interconnection information of said first step is generated from said design data.

17. A method for designing a semiconductor integrated circuit according to claim 1 wherein a net list descriptive of interconnection information of logic cells is inputted and wherein said logic cell information of said first step is generated from said net list.

18. A method for designing a semiconductor integrated circuit according to claim 1 wherein a schematic that represents interconnection information of logic cells is inputted and wherein said logic cell information of said first step is generated from said schematic.

19. A method for designing a semiconductor integrated circuit according to any one of claims 16, 17 and 18 wherein said logic cell interconnection information generated from said register-transfer-level design data, from said net list, or from said schematic is optimized and wherein said optimized information is used as said logic cell interconnection information of said first step.

20. A method for designing a semiconductor integrated circuit according to either of claims 1 or 2, further comprising a third step that includes:

checking each of said registers as to whether each of said registers provides a signal to said mapped or remapped second-type combinational circuit; and

mapping a register in said registers which is judge as a register which provides a signal to said mapped or remapped second-type combinational circuit into a register which is driven by a voltage from a voltage source including said high-voltage source, and mapping a register in said registers which is judge as a register which does not provide a signal to said mapped or remapped second-type combinational circuit into a register which is driven by a low voltage from said low-voltage source.

21. A method for designing a semiconductor integrated circuit according to claim 20 further including, after said third step, the step of:

verifying each said register'"'"'s timing.

22. A method for designing a semiconductor integrated circuit having a plurality of combinational circuits each of which includes a signal propagation path and having registers which are provided at stages respectively preceding and succeeding at least one of said plurality of combinational circuits, said method comprising:

a first step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay not more than a design delay upper limit, said combinational circuit into a combinational circuit of a first type driven by a low voltage from a low-voltage source;

a second step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay above the design delay upper limit, said combinational circuit into a combinational circuit of a second type driven by a high voltage from a high-voltage source;

and a third step of mapping each said register into a register driven by a low voltage from said low-voltage source;

wherein the difference in electric potential between a high voltage from said high-voltage source and a low voltage from said low-voltage source is held at a value below the threshold voltage of transistors forming said combinational circuits and registers.

23. A method for designing semiconductor integrated circuit according to claim 22,

wherein an internal part of said second-type combinational circuit is driven by a high voltage from said high-voltage source and the remaining internal part of said second-type combinational circuit is driven by a low voltage from said low-voltage source.

24. A method for designing a semiconductor integrated circuit according to claim 22 or claim 23;

said first step including;

mapping all of said plural combinational circuits into combinational circuits of the first type and mapping all of said plural registers into registers driven by a low voltage from said low-voltage source; and

determining whether there exists a combinational circuit in said mapped first-type combinational circuits that has a signal propagation delay above the design delay upper limit, and if such a combinational circuit is found to exist, remapping said combinational circuit into a combinational circuit of the second type.

25. A method for designing a semiconductor integrated circuit according to claim 22 or claim 23,

said first step including:

estimating, by making use of a combinational circuit of the first type and a register driven by a low voltage from said low-voltage source, a sum of signal propagation delays of said first-type combinational circuit and said register;

checking if said sum exceeds the design delay upper limit;

mapping, if said sum is found to be below the design delay upper limit, said first-type combinational circuit into a combinational circuit of the first type; and

mapping, if said sum is found to be above the design delay upper limit, said first-type combinational circuit into a combinational circuit of the second type.

26. A method for designing a semiconductor integrated circuit having a plurality of combinational circuits each of which includes a signal propagation path and having registers which are provided at stages respectively preceding and succeeding at least one of said plurality of combinational circuits, said method comprising:

a first step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay not more than a design delay upper limit, said combinational circuit into a combination circuit of a first type driven by a low voltage from a low-voltage source; and

a second step of mapping, when there exists a combinational circuit in said plural combinational circuits of which signal propagation path has a signal propagation delay above the design delay upper limit, said combinational circuit into a combinational circuit of a second type of which part is driven by a high voltage from a high-voltage source and of which remaining part of said combinational circuit is driven by a low voltage from said low-voltage source in order that the signal propagation path of said combinational circuit has a signal propagation delay below the design delay upper limit;

wherein said second step further includes;

(i) setting a plurality of windows each having a specified size and serving as a search range in a combinational circuit of which signal propagation path has a signal propagation delay above the design delay upper limit, said combinational-circuit-elements; and

(ii) selecting from among said plural windows a window that contains a group of combinational-circuit-elements of said elements whose total area or total delay is the smallest, and mapping said combinational-circuit-elements of said group into said part of said second-type combinational circuit.

27. A method for designing a semiconductor integrated circuit according to claim 26 wherein said window size is calculated based on said signal propagation delay time and said design delay upper limit.

28. A semiconductor integrated circuit having a plurality of combinational circuits each of which includes a signal propagation path and having registers which are provided at stages respectively preceding and succeeding at least one of said plurality of combinational circuits,

wherein:

(i) said plural combinational circuits are formed by combinational circuits of a first type driven by a low voltage from a low-voltage source and combinational circuits of a second type driven by a high voltage from a high-voltage source;

(ii) each of said plural registers is formed by a register driven by a low voltage from said low-voltage source; and

(iii) the difference in electric potential between a high voltage from said high-voltage source and a low voltage from said low-voltage source is held at a value below the threshold voltage of transistors forming said combinational circuits and registers.

29. A semiconductor integrated circuit according to claim 28 wherein an internal part of said second-type combinational circuit is driven by a high voltage from said high-voltage source and the remaining internal part thereof is driven by a low voltage from said low-voltage source.

30. A semiconductor integrated circuit according to claim 28 or claim 29 further comprising clock supply means which is driven by a low voltage from said low-voltage source and which applies a clock signal to each said register.

31. A semiconductor integrated circuit according to claim 28 or claim 29 wherein each said register is formed by a flip-flop circuit,

said flip-flop circuit including:

a master latch and a slave latch which are driven by a low voltage from said low-voltage source and which are connected in series.

32. A semiconductor integrated circuit according to claim 28 or claim 29 wherein each said register is formed by a latch circuit that has a latch section driven by a low voltage from said low-voltage source.