Semiconductor memory having NAND cell array and method of making thereof

• US 5,926,415 A
• Filed: 06/06/1997
• Issued: 07/20/1999
• Est. Priority Date: 06/07/1996
• Status: Expired due to Term

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Shin, Bong-Jo
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US08/867,429
• Time in Patent Office: 774 Days
• Field of Search: 365/185.17, 365/185.11, 365/230.03, 365/63, 365/72, 438/128, 438/129, 438/257
• US Class Current: 365/185.17
• CPC Class Codes: G11C 17/123 comprising cells having several storage transistors connected in series

Abstract

A NAND cell memory block array includes word lines and active regions arranged in X and Y directions. When a voltage of Vcc is applied to the word lines arranged in the X direction, a voltage of -Vcc is applied to the word lines arranged in the Y direction to turn off all transistors placed under the word lines arranged in the Y direction, thereby blocking the current path of the transistor. When a voltage of Vcc is applied to the word lines arranged in the Y direction, a voltage of -Vcc is applied to the word lines arranged in the X direction to turn off all transistors placed under the word lines arranged in the X direction, thereby blocking the current path of the transistor. The memory blocks arranged in the X and Y direction interweave or interleave with each other such that integration density can be doubled.

Claims

1. A NAND cell memory block array comprising:

first and second pluralities of memory blocks perpendicularly arranged in first and second directions, each of said first and second pluralities of memory blocks having a plurality of transistors, said transistors being serially connected to one another.

2. The NAND cell memory block array of claim 1, wherein said first plurality of memory blocks arranged in said first direction are connected to each bit line in pairs, said second plurality of memory blocks arranged in said second direction being connected to each bit line in pairs.

3. The NAND cell memory block array of claim 1, wherein said transistors are one of NMOS enhancement transistors and NMOS depletion transistors, said depletion transistor'"'"'s threshold voltage being approximately -1 v.

4. A method for forming a NAND cell memory block array, comprising the steps of:

(a) forming a field insulating layer to perpendicularly arrange active regions in first and second directions, said active region having the shape of strip;

(b) forming an impurity region in a portion in which a depletion transistor is formed;

(c) forming a first gate in the first direction;

(d) forming an insulating layer, and forming a second gate perpendicular to said first direction; and

(e) implanting impurities into said active region placed on both sides of said first and second gate lines, to form source and drain regions.

5. The method of claim 4, wherein, in said step (a), said field insulating layer is not formed on one edge of said active region to connect two active regions at their edges.

6. The method of claim 4 further comprising the step of ion implantation for controlling the threshold voltage of said depletion transistor prior to step (b).

7. The method of claim 6, wherein ion implantation for coding data to a NAND cell is carried out together with said ion implantation for controlling the threshold voltage.

8. The method of claim 4 further comprising the step of ion implantation for coding data to a NAND cell after step (e).

9. The method of claim 4 further comprising the steps of forming an insulating layer, forming a contact hole, and depositing and patterning a conductive material to form a conductive line after step (e).

10. The method of claim 9, wherein said insulating layer is formed of a silicon oxide layer, said conductive material is metal, and said steps of forming an insulating layer, forming a contact hole, and depositing and patterning a conductive material to form a conductive line are carried out two times, to form first and second metal lines.

11. A memory array comprising:

a first plurality of memory blocks arranged in a first direction; and

a second plurality of memory blocks arranged in a second direction which is different from the first direction, wherein each memory block includes a pair of memory sub-blocks, and each memory sub-block of said first plurality of memory blocks intersects each memory sub-block of said second plurality of memory blocks.

12. The memory array of claim 11, wherein each memory sub-block comprises a plurality of transistors coupled in series, and each pair of memory sub-blocks is coupled to a bit line.

13. The memory device of claim 11, wherein said first and second pluralities of memory blocks intersect at substantially at a right angle.

14. The memory array of claim 12, wherein said plurality of transistors comprises at least one of an enhancement mode transistor and a depletion mode transistor.