RISC86 instruction set

• US 5,926,642 A
• Filed: 05/16/1996
• Issued: 07/20/1999
• Est. Priority Date: 10/06/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Favor, John G.
• Primary Examiner(s): SHAH, ALPESH
• Application Number:
  US08/649,983
• Time in Patent Office: 1,160 Days
• Field of Search: 395/800.01, 395/800.23, 395/800.32, 395/800.41, 395/200.3, 395/200.33, 395/200.53, 395/670, 395/376, 395/384-386
• US Class Current: 712/1
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01
• CPC Class Codes: G06F 9/30152 Determining start or end of instruction; determining instruction length
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/324 using program counter relative addressing
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address.

Claims

1. A network server comprising:

a superscalar processor including;

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, each code in an instruction class having a mutually-consistent definition of defined-usage bit-fields, the instruction classes including;

a register operation (Regop) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands; and

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data;

a memory;

a processor bus coupled between the memory and the superscalar processor;

a local bus and an I/O bus;

first and second bridges, respectively coupling the processor bus to the local bus and the local bus to the I/O bus; and

a LAN adapter coupled to one of the local bus and the I/O bus.

2. A network server, as recited in claim 1, further comprising:

a data storage device coupled to one of the local bus and the I/O bus.

3. A network server, as recited in claim 2, wherein the data storage device comprises a hard disk.

4. A network server, as recited in claim 3, wherein the hard disk is selected from the group consisting of an IDE disk, an enhanced IDE disk, an ATA disk, an ESDI disk, and a SCSI disk.

5. A network server, as recited in claim 2, wherein the data storage device comprises a tape unit.

6. A network server, as recited in claim 5, wherein the tape unit is selected from the group consisting of an IDE tape unit, an enhanced IDE tape unit, an ATA tape unit, an ESDI tape unit, and a SCSI tape unit.

7. A network server, as recited in claim 2, wherein the data storage device comprises a CD-ROM.

8. A network server, as recited in claim 7, wherein the CD-ROM is selected from the group consisting of an IDE CD-ROM, an enhanced IDE CD-ROM, an ATA CD-ROM, an ESDI CD-ROM, and a SCSI CD-ROM.

9. A network server, as recited in claim 2, wherein the storage device comprises a jukebox.

10. A network server, as recited in claim 2, wherein the storage device comprises a RAID.

11. A network server, as recited in claim 2, wherein the storage device comprises a flash memory.

12. A network server, as recited in claim 1, wherein the LAN adapter is selected from the group consisting of a baseband network LAN adapter, a broadband network LAN adapter, a token passing network LAN adapter, a token ring network LAN adapter, a 10base-T network LAN adapter, and an ethernet LAN adapter.

13. A network server, as recited in claim 1, wherein the local bus comprises a VL bus.

14. A network server, as recited in claim 1, wherein the local bus comprises a PCI bus.

15. A network server, as recited in claim 1, wherein the I/O bus is selected from the group consisting of an ISA bus, an EISA bus, a Micro Channel Architecture Bus, and a local bus.

16. A network server, as recited in claim 1, further comprising:

a communications device coupled to one of the local bus and the I/O bus.

17. A network server, as recited in claim 16, wherein the communications device comprises one of a modem, a faxmodem, and an integrated telephony device.

18. A network server, as recited in claim 17, wherein the communications device further comprises a printed circuit card coupled to one of the local bus and the I/O bus via a modular connector.

19. A network server, as recited in claim 17, wherein the communications device is coupled to one of the local bus and the I/O bus via a serial interface.

20. A network server, as recited in claim 1, further comprising:

an I/O device coupled to one of the local bus and the I/O bus.

21. A network server, as recited in claim 20, wherein the I/O device is selected from the group consisting of a text display adapter, a graphics adapter, a 3-D graphics adapter, a SVGA display adapter, an XGA adapter, a display adapter supporting VESA graphics standards, a CGA adapter, an adapter supporting Hercules graphics standards.

22. A network server, as recited in claim 20, wherein the I/O device is selected from the group consisting of a pointing device, a mouse, a trackball, and a keyboard.

23. A network server comprising:

a superscalar processor including;

a source of CISC-like instructions;

a RISC-like processor core for executing a plurality of RISC-like operations in parallel; and

a decoder coupling the source of CISC-like instructions to the RISC-like processor core, the decoder for converting CISC-like instructions into operations of a RISC-like instruction set including;

a plurality of mutually-uniform bit-length instruction codes, each code being divided into a plurality of defined-usage bit fields and the codes being classified into a plurality of instruction classes, each code in an instruction class having a mutually-consistent definition of defined-usage bit-fields, the instruction classes including;

a register operation (Regop) class including arithmetic operations, shift operations and move operations and having defined-usage bit-fields including an operation type field, three operand bit-fields for designating a first source operand, a second source operand and a destination operand, a bit-field for designating a data size of the operands; and

a load-store operation (LdStOp) class including load and store operations and having defined-usage bit-fields including an operation type field, a plurality of bit-fields for designating a load-store address in memory, a bit-field for designating a data source-destination register for sourcing-receiving data from the load-store address in memory, and a bit-field for designating a data size of the source-destination data; and

a LAN adapter coupled to the superscalar processor.

24. A network server, as recited in claim 23, wherein the LAN adapter is selected from the group consisting of a baseband network LAN adapter, a broadband network LAN adapter, a token passing network LAN adapter, a token ring network LAN adapter, a 10base-T network LAN adapter, and an ethernet LAN adapter.

25. A network server, as recited in claim 23, further comprising a hard disk coupled to the superscalar processor.

26. A network server, as recited in claim 25, wherein the hard disk is selected from the group consisting of an IDE disk, an enhanced IDE disk, an ATA disk, an ESDI disk, and a SCSI disk.

27. A network server, as recited in claim 23, further comprising a tape unit coupled to the superscalar processor.

28. A network server, as recited in claim 27, wherein the tape unit is selected from the group consisting of an IDE tape unit, an enhanced IDE tape unit, an ATA tape unit, an ESDI tape unit, and a SCSI tape unit.

29. A network server, as recited in claim 23, further comprising a CD-ROM coupled to the superscalar processor.

30. A network server, as recited in claim 29, wherein the CD-ROM is selected from the group consisting of an IDE CD-ROM, an enhanced IDE CD-ROM, an ATA CD-ROM, an ESDI CD-ROM, and a SCSI CD-ROM.

31. A network server, as recited in claim 23, further comprising a jukebox coupled to the superscalar processor.

32. A network server, as recited in claim 23, further comprising a RAID coupled to the superscalar processor.

33. A network server, as recited in claim 23, further comprising a flash memory coupled to the superscalar processor.

34. A network server, as recited in claim 23, further comprising a modem coupled to the superscalar processor.

35. A network server, as recited in claim 23, further comprising a faxmodem coupled to the superscalar processor.

36. A network server, as recited in claim 23, further comprising an integrated telephony device coupled to the superscalar processor.

37. A network server, as recited in claim 23, further comprising a display adapter coupled to the superscalar processor, the display adapter selected from the group consisting of a text display adapter, a graphics adapter, a 3-D graphics adapter, a SVGA display adapter, an XGA adapter, a display adapter supporting VESA graphics standards, a CGA adapter, an adapter supporting Hercules graphics standards.

38. A network server, as recited in claim 23, further comprising an I/O device coupled to the superscalar processor, the I/O device selected from the group consisting of a pointing device, a mouse, a trackball, and a keyboard.