Semiconductor device and a manufacturing method thereof

• US 5,926,694 A
• Filed: 07/11/1997
• Issued: 07/20/1999
• Est. Priority Date: 07/11/1996
• Status: Expired due to Term

• Current Assignee: PFU Limited (Fujitsu Limited)
• Original Assignee: PFU Limited (Fujitsu Limited)
• Inventors: Matsuda, Kenji, Chigawa, Yasuhide, Fujiyama, Ippei
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): JONES, JOSETTA I
• Application Number:
  US08/891,493
• Time in Patent Office: 739 Days
• Field of Search: 438/107, 438/108, 438/106, 438/118
• US Class Current: 438/106
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

A manufacturing method of a semiconductor device for mounting an LSI bare-chip component, or a bare chip, on a printed circuit board, or a substrate, with flip-chip bonding technology, that includes a recess forming step of forming recesses on substrate pads of the substrate, an adhesive coating step of applying adhesive to a location on the substrate at which the bare chip is to be placed, a chip mounting step of placing the bare chip on the substrate while aligning positions of the bumps formed on the chip pads of the bare chip and the substrate pads of the substrate, and an adhesive hardening step of hardening the applied adhesive.

Claims

1. A manufacturing method of a semiconductor device comprising a bare chip having a plurality of chip pads and a substrate having a plurality of substrate pads, said method comprising:

a recess forming step for forming a recess by exerting a pushing force at a location of a substrate pad of said substrate corresponding to one or a plurality of chip pads of said bare chip;

an adhesive coating step for applying adhesive to a location of said substrate at which said bare chip is disposed;

a bare chip mounting step for placing said bare chip on said substrate by positioning bumps formed on said chip pads of said bare chip on said substrate pad of said substrate; and

an adhesive hardening step for hardening said applied adhesive.

2. A manufacturing method of a semiconductor device according to claim 1, further comprising:

a composite step for placing said bare chip on said substrate to which said adhesive has been applied while positioning said bumps on said substrate pads of said substrate, forcing said placed bare chip onto said substrate until each of said substrate pads of said substrate is recessed, and hardening said applied adhesive during said pushing process,

wherein after said adhesive coating step, said recess forming step, said bare chip mounting step, and said adhesive hardening step are carried out simultaneously in said composite step.

3. A manufacturing method of a semiconductor device according to claim 1, wherein said recess is formed on said substrate pads in said recess forming step by forcing said bare chip on which said bumps have been formed onto said substrate pads,

and wherein said adhesive coating step, said bare chip mounting step, and said adhesive hardening step are sequentially carried out after said recess forming step.

4. A manufacturing method of a semiconductor device according to claim 1, wherein said recess is formed on said substrate pads in said recess forming step using a jig having projections corresponding to locations of said bumps of said bare chip, and forcing said jig onto said substrate pads of said substrate,

and wherein said adhesive coating step, said chip mounting step, and said adhesive hardening step are sequentially carried out after said recess forming step.

5. A manufacturing method of a semiconductor device according to claim 4, wherein said jig includes a projection having a ridge of a predetermined length, and is forced onto said substrate pads of said substrate.

6. A manufacturing method of a semiconductor device according to claim 4, wherein said jig includes a plurality of projections arranged at certain intervals, and is forced onto said substrate pads of said substrate.

7. A manufacturing method of a semiconductor device according to claim 4, wherein said jig is kept at a high temperature so that said jig is prevented from cooling below a predetermined temperature between recess forming steps using said jig.

8. A manufacturing method of a semiconductor device according to claim 1, wherein a pushing force is exerted after said substrate is heated above a temperature at which an elasticity modulus of said substrate is lowered in said recess forming step, and then said substrate is cooled.

9. A manufacturing method of a semiconductor device according to claim 8, wherein said substrate is heated before said pushing force is applied.

10. A manufacturing method of a semiconductor device according to claim 8, wherein a pushing force is removed from said substrate before said cooling is completed.

11. A manufacturing method of a semiconductor device according to claim 1, wherein said bare chip is placed on said substrate under pressure in said bare chip mounting step, and

said adhesive hardening step is carried out by applying pressure and heat to harden said adhesive using a process different from said bare chip mounting step.

12. A manufacturing method of a semiconductor device according to claim 1, wherein a material having high elastic deformability is used for said substrate.

13. A manufacturing method of a semiconductor device according to claim 2, wherein said applied adhesive is hardened by by being heated to a predetermined temperature in said composite step.

14. A manufacturing method of a semiconductor device according to claim 4, wherein said substrate is heated above a temperature at which an elasticity modulus of said substrate is lowered in said composite step.

15. A manufacturing method of a semiconductor device according to claim 2, wherein said bare chip is forced onto said substrate with a predetermined pushing force in said composite step.

16. A manufacturing method of a semiconductor device according to claim 2, wherein air bubbles contained in adhesive to be applied in said composite step are removed by rotating said adhesive in a vacuum in said adhesive coating step.

17. A manufacturing method of a semiconductor device according to claim 1, wherein said substrate is heated so that viscosity of said adhesive applied in said adhesive coating step is lowered.

18. A manufacturing method of a semiconductor device according to claim 1, wherein a plurality of locations, including a center point and corner points of areas at which said bare chip is to be placed, are set as locations to which said adhesive is applied, and said adhesive is applied to said locations with predetermined coating amounts of said adhesive which are gradually reduced as a distance from said center point increases in said adhesive coating step.

19. A manufacturing method of a semiconductor device according to claim 1, wherein a surface of said substrate pads of said substrate is roughened.

20. A manufacturing method of a semiconductor device according to claim 1, wherein dimensional values of said substrate pads of said substrate are measured, and the pushing force of said recess forming step is determined based on said measured dimensional values, so that said substrate is forced in accordance with said determined pushing force.

21. A manufacturing method of a semiconductor device according to claim 2, wherein said bare chip is initially forced onto said substrate by setting said pushing force to a smaller value, and

said pushing force is increased to a predetermined value and said bare chip is forced onto said substrate prior to the hardening of said adhesive in said composite step.

22. A manufacturing method of a semiconductor device according to claim 2, wherein a recessed amount corresponding to the recess of said substrate pads in said composite step is measured allowing for a collapsed amount of said bumps, and said bare chip is forced onto said substrate until said recessed amount reaches a predetermined value.

23. A manufacturing method of a semiconductor device according to claim 22, wherein a pushing force is applied to each of said bumps prior to said composite step, whereby a height of each of said bumps prevents deforming.

24. A manufacturing method of a semiconductor device according to claim 22, wherein said bare chip is forced onto said substrate in said composite step while increasing said pushing force by stages in accordance with increases in temperature of said substrate until the recessed amount of said substrate pads reaches a predetermined value.