LDD device having a high concentration region under the channel

• US 5,926,703 A
• Filed: 01/21/1997
• Issued: 07/20/1999
• Est. Priority Date: 06/16/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Joachim, Hans-Oliver, Yamaguchi, Yasuo, Inoue, Yasuo
• Primary Examiner(s): Booth, Richard A
• Application Number:
  US08/785,277
• Time in Patent Office: 910 Days
• Field of Search: 438/151-157, 438/161-166, 438/305
• US Class Current: 438/163
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1×10¹⁸ /cm³ introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6'"'"') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'"'"'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'"'"'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a base body including a semiconductor substrate of a first conductivity type and having a first impurity concentration, an insulating layer formed on said semiconductor substrate, and a semiconductor layer formed on said insulating layer;

(b) selectively forming an insulating film on said semiconductor layer;

(c) forming a conductive layer on said insulating film;

(d) forming a resist on said conductive layer and patterning the resist into a predetermined form;

(e) performing an etching process to said conductive layer using said resist as a mask, said remaining conductive layer and said insulating film being defined as a gate electrode and a gate insulating film, respectively, said semiconductor layer being defined as a channel formation region in a region under said gate electrode and being defined as electrode regions in other region;

(f) implanting impurities of said first conductivity type with predetermined implantation energy from above to form a high concentration region having a second impurity concentration higher than said first impurity concentration in said semiconductor substrate, said high concentration regions being formed from under said channel formation region to under said electrode regions, said high concentration region being formed in a surface of said semiconductor substrate under said channel formation region, and in a region at a predetermined depth from the surface of said semiconductor substrate under said electrode regions;

(g) introducing impurities of the second conductivity type into said semiconductor layer using said gate electrode as a mask;

(h) forming first and second sidewalls on both sides of said gate electrode; and

(i) introducing impurities of a second conductivity type into said semiconductor layer using said gate electrode and said first and second sidewalls as masks, said semiconductor layer being defined as first and second additional semiconductor regions of the second conductivity type in regions under said first and second sidewalls, and defined as first and second semiconductor regions of the second conductivity type in regions adjacent to said first and second additional semiconductor regions, respectively, on sides opposite to said channel formation region, and a predetermined voltage is applied to said gate electrode to cause a current to flow between said first semiconductor region and said second semiconductor region through said channel formation region.

2. The method of manufacturing a semiconductor device according to claim 1, wherein said step (f) is carried out without removing said resist formed in said step (e).

3. The method of manufacturing a semiconductor device according to claim 1, wherein said steps (f)-(i) are carried out in the order of (f), (g), (h), (i).

4. The method of manufacturing a semiconductor device according to claim 1, wherein said steps (f)-(i) are carried out in the order of (g), (h), (i), (f).

5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step (j) of introducing impurities of the first conductivity type or the second conductivity type into said semiconductor layer, which is performed after said step (a).

6. The method of manufacturing a semiconductor device according to claim 1, wherein

said conductive layer is formed of first and second partial conductive layers, and

said step (c) comprises the steps of

(c-1) forming said first partial conductive layer on said insulating film and

(c-2) forming said second partial conductive layer on said first partial conductive layer, one of said first and second partial conductive layers being a refractory metal layer.

7. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a base body including a semiconductor substrate of a first conductivity type and having a first impurity concentration, an insulating layer formed on said semiconductor substrate, and a semiconductor layer formed on said insulating layer

(b) forming a resist on said semiconductor layer and patterning to provide an opening in the center of the first resist;

(c) introducing impurities of said first conductivity type using said first resist as a mask to form a high concentration region having a second impurity concentration higher than said first impurity concentration in the surface of said semiconductor substrate under the opening of said resist;

(d) selectively forming an insulating film on said semiconductor layer;

(e) forming a conductive layer on said insulating film;

(f) forming a second resist on said conductive layer and patterning the second resist into a predetermined form;

(g) performing an etching process to said conductive layer using said second resist as a mask, said remaining conductive layer and said insulating film being defined as a gate electrode and a gate insulating film, respectively, said semiconductor layer being defined as a channel formation region in a region under said gate electrode and defined as electrode regions in other regions;

(h) introducing impurities of a second conductivity type into said semiconductor layer using said gate electrode as a mask;

(i) forming first and second sidewalls on both sides of said gate electrode, said first and second sidewalls being formned so that said high concentration region is located to extend only from under said channel formation region to under parts of respective said first and second sidewalls; and

(j) introducing impurities of the second conductivity type into said semiconductor layer using said gate electrode and said first and second sidewalls as masks, said semiconductor layer being defined as first and second additional semiconductor regions of the second conductivity type under said first and second sidewalls, respectively, and defined as first and second semiconductor regions of the second conductivity type in regions adjacent to said first and second additional semiconductor regions, respectively, on sides opposite to said channel formation region, and a predetermined voltage is applied to said gate electrode to cause a current to flow between said first semiconductor region and said second semiconductor region through said channel formation region.