Method for generating a clock signal for use in a data receiver, clock generator, data receiver and remote controlled access system for vehicles

• US 5,928,293 A
• Filed: 04/29/1997
• Issued: 07/27/1999
• Est. Priority Date: 04/30/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Leclercq, Pascal, Jobling, David Trevor, Pilloud, Olivier, Tran, Laurent
• Primary Examiner(s): Cuchlinski, Jr., William A
• Assistant Examiner(s): ARTHUR JEANGLAUDE, GERTRUDE
• Application Number:
  US08/827,991
• Time in Patent Office: 819 Days
• Field of Search: 701/2, 370/324, 375/253, 375/354, 375/355, 375/333, 375/359, 375/361, 375/365
• US Class Current: 701/2
• CPC Class Codes: G07C 2009/00793 by Hertzian waves
• CPC Class Codes: G07C 2209/06 Involving synchronization or resynchronization between transmitter and receiver; reordering of codes
• CPC Class Codes: G07C 9/00182 operated with unidirectional data transmission between data carrier and locks
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A data receiver is arranged to receive data comprising a sync word having a predetermined data frequency (f_tx) and predetermined value. A clock signal (SCLK) is generated which is substantially synchronised with the received data. The n clocks (CLK1-CLK8) are generated, each of the n clocks having a frequency (fclk) which is substantially the predetermined data frequency (f_tx) and is out of phase with an adjacent clock of the n clocks by 1/n of a clock period. The sync word is sampled using each of the n clocks to determine which one of the n clocks is optimally synchronised with the sync word and to provide the determined one of the n clocks at an output (18). The determined one of the n clocks provides the clock signal (SCLK).

Claims

1. A method for generating a clock signal for use in a data receiver, the clock signal being substantially synchronised with data received by the data receiver, the received data comprising a sync word having a predetermined data frequency and predetermined value and being Manchester coded so that each bit of the sync word comprises a logic `1` in one phase of a clock period and a logic `0` in an anti-phase of the clock period, the method comprising the steps of:

generating n clocks, each of the n clocks having a frequency which is substantially the predetermined data frequency and being out of phase with an adjacent clock of the n clocks by 1/n of the clock period, each of the n clocks further having one other clock of the n clocks in anti-phase therewith, wherein the data receiver comprises register means comprising n registers, each of the n registers being clocked by a respective one of the n clocks, and having an anti-phase register clocked by an anti-phase clock;

shifting the received data into each register of the n registers in parallel according to the respective clock of the n clocks;

comparing the contents of each register with a Manchester coded comparison word having the predetermined value and providing a comparison signal for each of the n registers, the comparison signal having a first logic state when the contents of the register match the comparison word and a second logic state when the contents of the register do not match the comparison word;

checking whether the contents of each register is inverted compared to the contents of its anti-phase register;

providing an output signal for each register, the output signal having a first logic state when the comparison signal for the register has a first logic state and the contents of the register is inverted compared to the contents of its anti-phase register, and a second logic state when the comparison signal of the register has a second logic state and/or the contents of the register is not inverted compared to the contents of its anti-phase register;

selecting one of the n clocks which clocks a register whose output signal has the first logic state; and

providing the selected one of the n clocks at an output, the selected one of the n clocks providing the clock signal.

2. A method according to claim 1 wherein the received data comprises a plurality of data packets, each comprising a sync word having the predetermined data frequency and the predetermined value, followed by real data, followed by a plurality of zeros or a plurality of ones, the method further comprising the steps of:

resetting the determined clock on receipt of the plurality of zeros or the plurality of ones; and

generating a clock signal which is substantially synchronised to the received data using the next sync word.

3. A method according to claim 1 wherein the selecting step comprises the steps of:

determining which clocks of the n clocks are valid according to the following rule;

if an output signal m has the first logic state, and second (m+2) and third (m+3) output signals in succession from the output signal both have the second logic state, then the clock associated with the output signal m is valid;

determining which of the determined valid clocks is the second last valid clock or the only valid clock; and

providing the second last valid clock or the only valid clock as the selected one of the n clocks.

4. A method according to claim 1 wherein n is at least four.

5. A method according to claim 1 wherein the frequency of each of the n clocks is equal to (1+p)*f_tx, where f_tx is the predetermined data frequency and p is a positive or negative number less than 1.

6. A clock generator for generating a clock signal for use in a data receiver, the clock signal being substantially synchronised with data received by the data receiver, the received data comprising a sync word having a predetermined data frequency and a predetermined value, and being Manchester coded so that each bit of the sync word comprises a logic `1` in one phase of a clock period and a logic `0` in an anti-phase of the clock period, the clock generator comprising:

means for generating n clocks, each of the n clocks having a frequency which is substantially the predetermined data frequency and being out of phase with an adjacent clock of the n clocks by 1/n of the clock period, each of the n clocks further having one other clock of the n clocks in anti-phase therewith;

register means coupled to receive the received data, the register means comprising;

n registers, each of the n registers being clocked by a respective one of the n clocks such that the received data is shifted into each register of the n registers in parallel according to the respective clock of the n clocks, each of the n registers having an anti-phase register clocked by an anti-phase clock,

n decode logic coupled to respective registers of the n registers, each decode logic for comparing the contents of the respective register with a Manchester coded comparison word having the predetermined value and providing a comparison signal at an output, the comparison signal having a first logic state when the contents of the respective register match the comparison word and a second logic state when the contents of the respective register do not match the comparison word, and

n logic gates for respective registers of the n registers, each logic gate being coupled to the decode logic of the respective register and to the decode logic of its anti-phase register for checking whether the contents of the respective register is inverted compared to the contents of its anti-phase register and for providing an output signal for the respective register, the output signal having a first logic state when the comparison signal for the register has a first logic state and the contents of the register is inverted compared to the contents of its anti-phase register, and a second logic state when the comparison signal of the register has a second logic state and/or the contents of the register is not inverted compared to the contents of its anti-phase register; and

logic means for selecting one of the n clocks which clocks a register whose output signal has the first logic state and for providing the selected one of the n clocks as the clock signal for use in the data receiver.

7. A clock generator according to claim 6 wherein the logic means comprises:

means for determining which clocks of the n clocks are valid according to the following rule;

if an output signal m has the first logic state, and second (m+2) and third (m+3) output signals in succession from the output signal both have the second logic state, then the clock associated with the output signal m is valid; and

means for determining which of the determined valid clocks is the second last valid clock or the only valid clock and providing the second last valid clock or the only valid clock as the selected one of the n clocks.

8. A clock generator according to claim 6 wherein n is at least four.

9. A clock generator according to claim 6 wherein the frequency of each of the n clocks is equal to (1+p)*f_tx, where f_tx is the predetermined data frequency and p is a positive or negative number less than 1.

10. A clock generator according to claim 6 further comprising a data recovery circuit having a data input for receiving the received data, a clock input for receiving the selected clock from the logic means, the data recovery circuit using the selected clock to provide the received data at an output, for use in the data receiver, which is substantially synchronised to the selected clock.

11. A data receiver for receiving data transmitted by a data transmitter, the data receiver comprising a clock generator for generating a clock signal for use in a data receiver, the clock signal being substantially synchronised with data received by the data receiver, the received data comprising a sync word having a predetermined data frequency and a predetermined value, and being Manchester coded so that each bit of the sync word comprises a logic `1` in one phase of a clock period and a logic `0` in an anti-phase of the clock period, the clock generator comprising:

means for generating n clocks, each of the n clocks having a frequency which is substantially the predetermined data frequency and being out of phase with an adjacent clock of the n clocks by 1/n of the clock period, each of the n clocks further having one other clock of the n clocks in anti-phase therewith;

register means coupled to receive the received data, the register means comprising;

n registers, each of the n registers being clocked by a respective one of the n clocks such that the received data is shifted into each register of the n registers in parallel according to the respective clock of the n clocks, each of the n registers having an anti-phase register clocked by an anti-phase clock,

n decode logic coupled to respective registers of the n registers, each decode logic for comparing the contents of the respective register with a Manchester coded comparison word having the predetermined value and providing a comparison signal at an output, the comparison signal having a first logic state when the contents of the respective register match the comparison word and a second logic state when the contents of the respective register do not match the comparison word, and

n logic gates for respective registers of the n registers, each logic gate being coupled to the decode logic of the respective register and to the decode logic of its anti-phase register for checking whether the contents of the respective register is inverted compared to the contents of its anti-phase register and for providing an output signal for the respective register, the output signal having a first logic state when the comparison signal for the register has a first logic state and the contents of the register is inverted compared to the contents of its anti-phase register, and a second logic state when the comparison signal of the register has a second logic state and/or the contents of the register is not inverted compared to the contents of its anti-phase register; and

logic means for selecting one of the n clocks which clocks a register whose output signal has the first logic state and for providing the selected one of the n clocks as the clock signal for use in the data receiver.

12. A data receiver according to claim 11 further comprising a state machine for determining the state of the data receiver, the state machine being clocked by the clock signal generated by the clock generator.

13. A remote controlled access system for vehicles comprising a data transmitter for transmitting a coded signal for locking or unlocking the doors of the vehicle, the system further comprising a data receiver for receiving data transmitted by a data transmitter, the data receiver comprising a clock generator for generating a clock signal for use in a data receiver, the clock signal being substantially synchronised with data received by the data receiver, the received data comprising a sync word having a predetermined data frequency and a predetermined value, and being Manchester coded so that each bit of the sync word comprises a logic `1` in one phase of a clock period and a logic `0` in an anti-phase of the clock period, the clock generator comprising:

means for generating n clocks, each of the n clocks having a frequency which is substantially the predetermined data frequency and being out of phase with an adjacent clock of the n clocks by 1/n of the clock period, each of the n clocks further having one other clock of the n clocks in anti-phase therewith;

register means coupled to receive the received data, the register means comprising;

n registers, each of the n registers being clocked by a respective one of the n clocks such that the received data is shifted into each register of the n registers in parallel according to the respective clock of the n clocks, each of the n registers having an anti-phase register clocked by an anti-phase clock,

n decode logic coupled to respective registers of the n registers, each decode logic for comparing the contents of the respective register with a Manchester coded comparison word having the predetermined value and providing a comparison signal at an output, the comparison signal having a first logic state when the contents of the respective register match the comparison word and a second logic state when the contents respective register do not match the comparison word, and

n logic gates for respective registers of the n registers, each logic gate being coupled to the decode logic of the respective register and to the decode logic of its anti-phase register for checking whether the contents of the respective register is inverted compared to the contents of its anti-phase register and for providing an output signal for the respective register, the output signal having a first logic state when the comparison signal for the register has a first logic state and the contents of the register is inverted compared to the contents of its anti-phase register, and a second logic state when the comparison signal of the register has a second logic state and/or the contents of the register is not inverted compared to the contents of its anti-phase register; and

logic means for selecting one of the n clocks which clocks a register whose output signal has the first logic state and for providing the selected one of the n clocks as the clock signal for use in the data receiver.

14. A remote controlled access system according to claim 13 wherein the coded signal for locking or unlocking the doors of the vehicle is a radio frequency signal.

15. A remote controlled access system according to claim 13 wherein the coded signal for locking or unlocking the doors of the vehicle is an infra-red signal.