Memory module having memory devices containing internal device ID registers and method of initializing same

• US 5,928,343 A
• Filed: 06/16/1998
• Issued: 07/27/1999
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/098,387
• Time in Patent Office: 406 Days
• Field of Search: 395/284, 395/828, 395/829, 711/170, 710/8, 710/9, 710/104, 365/230.03
• US Class Current: 710/104
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for assigning identification values to memories. A master resets identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master. The master places a first identification value on a data bus coupled to the master and to the first and second memories. The first memory stores the first identification value on the data bus as an identifier for the first memory when the master sends a first storage signal to the first memory via the daisy-chained line. The master places a second identification value on the data bus. The second memory stores the second identification value on the data bus as an identifier for the second memory when the master sends a second storage signal to the second memory via the daisy-chained line.

Claims

1. A method for assigning identification values to memories, comprising the steps of:

(1) having a master reset identifiers of a first memory and a second memory by sending a reset signal on a line that is coupled in a daisy-chained manner to the first and second memories and also coupled to the master;

(2) having a master send first and second identification values on the daisy-chained line to the first and second memories;

(3) having the first memory store at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory;

(4) having the second memory store at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.

2. An apparatus for assigning identification values to memories, the apparatus comprising:

(1) a daisy-chained line coupled to a master, a first memory and a second memory;

(2) a data bus coupled to the master, the first memory, and the second memory;

(3) reset circuitry for sending a reset signal from the master to the first and second memories via the daisy-chained line and for resetting identifiers of the first and second memories in response to the reset signal;

(4) circuitry within the master for generating first and second identification values and sending them to the first and second memories via the daisy-chained line;

(5) circuitry within the first memory for storing at a first predetermined time the first identification value on the daisy-chained line as an identifier for the first memory; and

(6) circuitry within the second memory for storing at a second predetermined time the second identification value on the daisy-chained line as an identifier for the second memory.

3. A memory module having a plurality of memory devices, the memory module comprises:

a bus having a plurality of signal lines including a reset signal line which is electrically connected to the plurality of memory devices;

a first memory device including;

at least one memory section having a plurality of memory cells which are accessed using address signals;

an internal register to store an identification value to identify the first memory device on the bus; and

interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the first memory device stores the identification value which identifies the first memory device on the bus; and

a second memory device including;

at least one memory section having a plurality of memory cells which are accessed using address signals;

an internal register to store an identification value to identify the second memory device on the bus; and

interface circuitry, coupled to the bus, to receive a reset request via the reset signal line wherein, in response to a received reset request, the internal register in the second memory device stores the identification value which identifies the second memory device on the bus.

4. The memory module of claim 3 wherein:

the internal register of the first memory device stores a unique identification value to identify the first memory device from thy plurality of memory devices, including the second memory device, on the bus; and

the internal register of the second memory device stores a unique identification value to identify the second memory device from the plurality of memory devices, including the first memory device, on the bus.

5. The memory module of claim 3 wherein the internal register of the first memory device stores an identification value to identify the first memory device and a plurality of memory devices, including the second memory device, on the bus.

6. The memory module of claim 3 wherein the bus includes a clock signal line for receiving an external clock signal and data lines for receiving the identification values.

7. The memory module of claim 6 wherein the first memory device includes a reset register coupled to the reset signal line to receive the reset signal.

8. The memory module of claim 7 wherein the reset register of the first memory device is clocked synchronously with respect to the external clock signal such that the reset signal is clocked through the reset register.

9. The memory module of claim 8 wherein the identification register of the first memory device stores the identification value while the reset signal is in the reset register of the first memory device.

10. The memory module of claim 9 wherein the internal register of the first memory device stores the identification value of the first memory device register after a predetermined number of clock cycles of the external clock signal and while the reset signal is in the reset register of the first memory device.

11. The memory module of claim 3 wherein the first and second memory devices receive the identification values on the reset signal line.

12. The memory module of claim 11 wherein the internal register of the first memory device stores the identification value which identifies the first memory device on the bus at a first predetermined time and the internal register of the second memory device stores the identification value which identifies the second memory device on the bus at a second predetermined time.

13. The memory module of claim 12 wherein the first and the second predetermined times are the same.

14. The memory module of claim 12 wherein the identification values are clocked along the reset signal line synchronously with respect to an external clock signal.

15. The memory module of claim 12 wherein the internal registers of the first and second memory device store the identification values after a predetermined number of clock cycles of an external clock signal.

16. The memory module of claim 12 wherein the first memory device includes a reset register coupled to the reset signal line to receive the identification value of the first memory device.

17. The memory module of claim 16 wherein the reset register is clocked synchronously with respect to an external clock signal.

18. The memory module of claim 16 wherein the identification register is coupled to the reset register to receive and store the identification value received by the reset register at the first predetermined time.

19. The memory module of claim 16 wherein the identification register is coupled to the reset register to receive and store the data in the reset register after a predetermined number of clock cycles of the external clock signal.

20. The memory module of claim 12 wherein the second memory device includes a reset register coupled to the reset signal line at an output of the reset register of the first memory device.

21. The memory module of claim 20 wherein the reset register of the second memory device is clocked synchronously with respect to the external clock signal.

22. The memory module of claim 21 wherein the identification register is coupled to the reset register to receive and store the data in the reset register at the second predetermined time.

23. The memory module of claim 22 wherein the first predetermined time and the second predetermined time are the same.

24. A method of assigning identification values to a plurality of memory devices disposed on a memory module, the plurality of memory devices include a first memory device having a programmable register for storing an identification value and second memory device having a programmable register for storing an identification value, wherein the memory module includes a bus to electrically connect the first and the second memory devices, wherein the bus includes a plurality of signal lines including a reset signal line which electrically connects the first and the second memory devices, a clock signal line for receiving an external clock signal, and data lines for receiving first and second identification values, the method comprising:

applying the first identification value on the data lines for a predetermined number of clock cycles of the external clock signal;

applying a reset signal to the first memory device wherein, in response to the reset signal received by the first memory device, the programmable register in the first memory device stores the first identification value;

applying the second information value on the data lines for the predetermined number of clock cycles of the external clock signal; and

applying a reset signal to the second memory device wherein, in response to the reset signal received by the second memory device, the programmable register in the second memory device stores the second identification value.

25. The method of claim 24 wherein:

the first identification value is a unique identification value which identifies the first memory device from the plurality of memory devices, including the second memory device, on the bus; and

the second identification value is a unique identification value which identifies the second memory device from the plurality of memory devices, including the first memory device, on the bus.

26. The method of claim 24 wherein the first identification value is a special identification value which identifies the first memory device and a plurality of memory devices, including the second memory device, on the bus.

27. A method of assigning identification values to first and second memory devices disposed on a memory module having a bus which electrically connects the first and the second memory devices, wherein the bus includes a plurality of signal lines including a daisy-chained signal line which electrically connects the first and the second memory devices in a daisy-chained manner, the method comprising:

applying first and second identification values on the daisy-chained signal line;

storing the first identification value in a programmable register in the first memory device at a first predetermined time; and

storing the second identification value in a programmable register in the second memory device at a second predetermined time.

28. The method of claim 27 wherein:

the first identification value is a unique identification value which identifies the first memory device from the plurality of memory devices on the bus; and

the second identification value is a unique identification value which identifies the second memory device from the plurality of memory devices on the bus.

29. The method of claim 27 wherein the first identification value is a special identification value which identifies the first memory device and a plurality of memory devices on the bus.