Serial data bus and use thereof

• US 5,928,344 A
• Filed: 06/12/1997
• Issued: 07/27/1999
• Est. Priority Date: 06/13/1996
• Status: Expired due to Fees

• Current Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Original Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Inventors: Stierli, Peter
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/873,668
• Time in Patent Office: 775 Days
• Field of Search: 395/280, 395/284, 395/285, 395/290, 395/293, 395/309
• US Class Current: 710/105
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/40163 by assigning priority to messages according to a message field
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54

Abstract

A serial data bus with a two-wire line and a plurality of bus nodes for the exchange of data messages in both directions between the bus nodes and a central unit connected to the bus and for the current supply of the bus nodes. Conflicts between data messages that appear simultaneously are resolved on the basis of the priority thereof. The bus is constructed in the manner of a multi-master system in which each bus and the central unit is a master, and the central unit provides the bus timing and controls the synchronization of the bus. Each bit transmission is divided up into a positive and a negative phase, the current supply of the bus nodes being effected in the positive phase and the data transmission being effected in the negative phase.

The bus is preferably used for a hazard-detection system wherein the bus nodes comprise a micro-controller and either are constituted by special detectors with integrated bus or comprise an interface for the connection of the detectors. Bus protocol and bus timing are coordinated with the micro-controllers in such a way that the latter can take over the operation of the bus.

Claims

1. A serial data bus for communicating data messages having a plurality of bits, said serial data bus comprising:

(a) a plurality of bus nodes, each of said bus nodes for functioning as a master;

(b) a central unit connected to said bus nodes for determining positive and negative phases of operation for said serial data bus, providing timing for said serial data bus, controlling the synchronization of said serial data bus, supplying current to said bus nodes during said positive phase, and for functioning as a master; and

(c) a two-wire line connecting said bus nodes with said central unit over which said data messages are communicated to and from said central unit and said bus nodes in a prioritized manner regardless of whether a previous data message is presently being communicated, and wherein each bit of said data messages is transmitted during said negative phase over said two-wire line.

2. The serial data bus according to claim 1, wherein said bus nodes and said central unit include switching means for switching over between said current supply and said data transmission, said switching means preferably consists of diodes.

3. The serial data bus according to claim 1, wherein said data messages include an event-driven, prioritized protocol.

4. The serial data bus according to claim 1, wherein said bus nodes are connected to said bus as T-pieces.

5. The serial data bus according to claim 1, wherein said data messages are effected in the form of voltage pulses when transmitted between said central unit and said bus nodes during said positive phase, and effected in the form of current pulses when transmitted between said bus nodes and said central unit during said negative phase, said data messages including said plurality of bits the level values thereof being determined by the duration of said voltage pulses when transmitted between said central unit and said bus nodes during said positive phase, and by the amplitude of said current pulses when transmitted between said bus nodes and said central unit during said negative phase.

6. The serial data bus according to claim 1, wherein said central unit and said bus nodes each include a comparator for determining the logic level of said plurality of bits contained within each of said data messages received by said central unit and said bus nodes.

7. The serial data bus according to claim 1, wherein said data messages include priority bits, control bits, address bits and optionally data bits.

8. The serial data bus according to claim 1, wherein said data messages include an arbitration field for determining a priority of said data messages, said arbitration field comprising:

(a) two priority bits;

(b) a central-unit bit for indication of a direction of each of said data messages, said direction being either from said central unit to said bus nodes, or from said bus nodes to said central unit;

(c) an address-mode bit, such that said address-mode bit, said central-unit bit and said priority bits comprise the first four bits of each of said data messages; and

(d) said address bits.

9. The serial data bus according to claim 8, wherein said arbitration field consists of arbitration field bits having arbitration bit values equal to logical "1'"'"'s" or "0'"'"'s," such that arbitration field bit values equal to "1" are dominant arbitration field bit values, said priority of data messages depending on the position of said dominant arbitration field bit values within said arbitration field.

10. The serial data bus according to claim 1, wherein said central unit is a main operating station of an intrusion-detection system for acquiring alarm and sabotage messages emanating from said bus nodes connected to said central unit, and for controlling the programming of said bus nodes for indication, alarm-raising and false alarms.

11. The serial data bus according to claim 1, wherein said central unit is a main operating station of a fire-detection system for acquiring alarm messages emanating from said bus nodes connected to said central unit, and for controlling the programming of said bus nodes for indication, alarm-raising and false alarms.

12. A hazard-detection method comprising:

prioritizing data messages on a serial data bus;

operating each of a plurality of bus nodes as a master;

operating a central unit as said master;

determining positive and negative phases of operation for said serial data bus;

providing timing for said serial data bus;

controlling the synchronization of said serial data bus;

supplying current to said bus nodes during said positive phase; and

transmitting said data messages during said negative phase between said central unit and said bus nodes in a prioritized manner regardless of whether a previous data message is presently being communicated.

13. The hazard-detection method of claim 12, wherein said step of operating said bus nodes includes operating detectors, one at each of said nodes, each of said detectors including a micro-controller and an interface for the connection of said detectors.

14. The hazard-detection method of claim 12, wherein said step of operating said bus nodes includes operating detectors, one at each of said nodes, each of said detectors including a micro-controller having an integrated bus.

15. The hazard detection method of claim 12, wherein said step of operating said detectors includes implementing a protocol and synchronizing the timing for said serial data bus such that each micro-controller can take over the operation of said serial data bus.