Field instrument with data bus communications protocol

• US 5,928,345 A
• Filed: 09/30/1996
• Issued: 07/27/1999
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: Rosemount Incorporated (Emerson Electric Company)
• Original Assignee: Rosemount Incorporated (Emerson Electric Company)
• Inventors: Warrior, Jogesh, Tetzlaff, David E., Maalouf, Gabriel A.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US08/723,688
• Time in Patent Office: 1,030 Days
• Field of Search: 395/285, 395/287, 395/829, 395/857, 709/208, 170/105-107, 170/110, 170/9, 340/825.07
• US Class Current: 710/107
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G05B 19/4185 characterised by the network communication
• CPC Class Codes: G05B 2219/25145 I-O communicates with local bus at one end and with fieldbus at other end
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention includes a process control instrument having an improved data bus protocol for facilitating communications between master and slave nodes. The process control instrument includes a microprocessor operating in accordance with the SPI data bus protocol, first and second peripheral devices, and a data bus coupled to the microprocessor and the first and second peripheral devices. The improved data bus protocol used in the process control instruments of the present invention provides numerous advantages such as reduced printed circuit board space requirements and greater interchangeability of peripheral and master node components.

Claims

1. A process control instrument comprising:

a microprocessor operating in accordance with the SPI data bus protocol;

a first peripheral device;

a second peripheral device; and

a data bus coupled to the microprocessor, to the first peripheral device, and to the second peripheral device, wherein the data bus includes a single chip select line coupled to chip select connections on each of the microprocessor, the first peripheral device and the second peripheral device, and wherein the data bus further includes a bi-directional master-in-slave-out (MISO) line coupled to the microprocessor, the first peripheral device and the second peripheral device.

2. The process control instrument of claim 1, wherein the microprocessor generates a signal on the single chip select line of the data bus to notify the first and second peripheral devices that the data bus is active.

3. The process control instrument of claim 1, wherein the first peripheral device transmits messages to the second peripheral device on the bi-directional MISO line.

4. The process control instrument of claim 1, and further comprising means for dynamically assigning addresses to the first and second peripheral devices for use in communicating on the data bus.

5. A process control instrument comprising:

a microprocessor operating in accordance with the SPI protocol;

a first peripheral device;

a second peripheral device; and

a data bus coupled to the microprocessor, to the first peripheral device and to the second peripheral device, wherein the data bus includes a bi-directional Master-In-Slave-Out (MISO) line coupled to MISO connections on each of the microprocessor, the first peripheral device and the second peripheral device.

6. The process control instrument of claim 5, wherein the bi-directional MISO line is adapted to carry serial data both from the first and second peripheral devices to the microprocessor, and between the first and second peripheral devices.

7. The process control instrument of claim 6 and further comprising a third peripheral device having a MISO connection coupled to the bi-directional MISO line of the data bus, wherein the first peripheral device broadcasts messages to both of the second and third peripheral devices simultaneously over the bi-directional MISO line.

8. The process control instrument of claim 6 and further comprising means for dynamically assigning addresses to each of the first and second peripheral devices for use in receiving messages over the data bus.

9. The process control instrument of claim 8, wherein each of the first and second peripheral devices has a priority associated therewith, wherein the one of the first and second peripheral devices having a higher priority assigns itself a first address and subsequently broadcasts the first address over the bi-directional MISO line to the microprocessor and to the other of the first and second peripheral devices having a lower priority.

10. The process control instrument of claim 9, wherein after the one of the first and second peripheral devices broadcasts the first address, the other of the first and second peripheral devices assigns itself a second address and subsequently broadcasts the second address over the bi-directional MISO line to the microprocessor and to the one of the first and second peripheral devices.

11. The process control instrument of claim 8, wherein each of the first and second peripheral devices includes interrupt generating circuits for generating interrupts, wherein the means for dynamically assigning addresses comprises:

an interrupt detection circuit associated with the microprocessor for detecting a first interrupt generated by one of the first and second peripheral devices on the data bus;

an address generating circuit associated with the microprocessor for generating a first address; and

an address transmitting circuit associated with the microprocessor for transmitting over the data bus the first address to the one of the first and second peripheral devices which generated the first interrupt and thereby assigning the first address to the one of the first and second peripheral devices which generated the first interrupt.

12. The process control instrument of claim 6, wherein the data bus includes a single chip select line coupled to chip select connections on each of the microprocessor, the first peripheral device and the second peripheral device.

13. A process control instrument, comprising:

a first slave node;

a second slave node; and

a master node, wherein the master node is coupled to the first and second slave nodes by a data bus, wherein the master node comprises;

an interrupt detection circuit for detecting a first interrupt generated by one of the first and second slave nodes on the data bus;

an address generating circuit for generating a first address in response to the first interrupt generated by the one of the first and second slave nodes; and

an address transmitting circuit for transmitting over the data bus the first address to the one of the first and second slave nodes which generated the first interrupt and thereby assigning the first address to the one of the first and second slave nodes which generated the first interrupt.

14. The process control instrument of claim 13, wherein the master node further comprises:

an interrupt detection circuit for detecting a second interrupt generated by the other of the first and second slave nodes on the data bus;

an address generating circuit for generating a second address in response to the second interrupt generated by the other of the first and second slave nodes; and

an address transmitting circuit for transmitting over the data bus the second address to the other of the first and second slave nodes which generated the second interrupt and thereby assigning the second address to the other of the first and second slave nodes which generated the second interrupt.

15. A system comprising:

a microprocessor operating in accordance with the SPI protocol;

a first peripheral device;

a second peripheral device;

a data bus coupled to the microprocessor, to the first peripheral device and to the second peripheral device; and

means for dynamically assigning addresses to each of the first and second peripheral devices for use in receiving messages over the data bus, wherein the means for dynamically assigning addresses is coupled to the data bus, wherein each of the first and second peripheral devices has a priority associated therewith, wherein the means for dynamically assigning addresses includes means for the one of the first and second peripheral devices having a higher priority to assign itself a first address and subsequently broadcast the first address over the data bus to the microprocessor and to the other of the first and second peripheral devices having a lower priority.

16. A method of communicating on a data bus in a process control instrument, comprising:

generating a chip select signal on a single chip select line of the data bus coupled to chip select inputs of each of first and second peripheral devices, wherein the chip select signal is generated by a microprocessor operating in accordance with the SPI data bus protocol to indicate that the data bus is active; and

transmitting data from one of the first and second peripheral devices to the other of the first and second peripheral devices over a master-in-slave-out (MISO) line of the data bus while the chip select signal is generated on the single chip select line coupled to chip select inputs of each of first and second peripheral devices.

17. A method of communicating on a data bus between first and second peripheral devices in a process control instrument, the method comprising:

transmitting data from a bi-directional master-in-slave-out (MISO) connection on the first peripheral device over a bi-directional MISO line on the data bus; and

receiving the data transmitted from the bi-directional MISO connection on the first peripheral device at a bi-directional MISO connection on the second peripheral device.