Compliant integrated circuit package and method of fabricating the same

• US 5,929,517 A
• Filed: 12/29/1994
• Issued: 07/27/1999
• Est. Priority Date: 12/29/1994
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Karavakis, Konstantine, Smith, John W., Mitchell, Craig, Distefano, Thomas H.
• Primary Examiner(s): VO, PETER DUNG BA
• Application Number:
  US08/365,749
• Time in Patent Office: 1,671 Days
• Field of Search: 29/841, 29/832, 29/856, 29/613, 29/844, 174/52.4, 174/52.3, 437/209, 437/221, 437/224, 437/211, 264/272.17, 257/684, 257/687, 257/688, 257/706, 257/707
• US Class Current: 257/707
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01061 Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.

Claims

1. A semiconductor chip package comprising:

a thermally conductive protective structure having front and back sides, a forward direction outwardly away from the front side of the structure and a rearward direction opposite to said forward direction, the protective structure defining an indentation open to the front of the structure and a flange surface at least partially surrounding the opening of the indentation and facing in said forward direction, said indentation extending into the protective structure in said rearward direction, said protective structure having an indentation rear surface at the rear of said indentation;

a chip disposed in the indentation, the chip having a front surface bearing a plurality of contacts and a back surface, the front surface of the chip facing in said forward direction, the back surface of said chip facing said indentation rear surface;

a first flexible dielectric circuit film having terminals thereon overlying the flange surface of the protective structure, each contact on the chip being electrically connected to at least one terminal;

a compliant material disposed between the first film and the flange surface; and

means for sealing the front of the protective structure to protect the chip against environment contamination, wherein the terminals are exposed at the front of the protective structure and are independently displaceable in said rearward direction towards the front side of the protective structure.

2. The package as claimed in claim 1, wherein the first film has a first surface facing away from the flange surface and a second surface facing toward the flange surface, and wherein the sealing means includes a dielectric mask layer extending across the first surface of the first film.

3. The package as claimed in claim 2, wherein the sealing means further including a compliant material disposed within the indentation of the protective structure substantially encapsulating the chip therein.

4. The package as claimed in claim 2, wherein the compliant material includes a plurality of compliant pads each positioned beneath or around at least one terminal.

5. The package as claimed in claim 1, wherein the first film has a bond window aligned with the chip, the package further comprising a second film having second terminals thereon electrically connected to the contacts on the chip, the second film overlying the chip within the bond window, the package further including compliant material disposed between the second film and the chip.

6. The package as claimed in claim 5, further including holding straps coupled between the first and second dielectric layers, and a means for electrically isolating terminals which are connected to the same contact on the chip.

7. The package as claimed in claim 5, wherein the compliant material includes a plurality of compliant pads each positioned beneath a respective terminal.

8. A method of fabricating a semiconductor chip package, comprising the steps of:

providing a thermally conductive protective structure having front and back sides, a forward direction outwardly away from the front side of the structure and a rearward direction opposite to said forward direction, the protective structure defining an indentation open to the front of the structure and a flange surface at least partially surrounding the opening of the indentation and facing in said forward direction, said indentation extending into the protective structure in said rearward direction, said protective structure having an indentation rear surface at the rear of said indentation;

disposing a chip within the indentation, the chip having a front surface bearing a plurality of contacts and a back surface, the front surface of the chip facing in said forward direction, the back surface of said chip facing said indentation rear surface;

placing a first flexible dielectric circuit film having terminals thereon overlying the flange surface of the protective structure, each terminal being electrically connected to one contact on the chip;

disposing a compliant material between the first film and the flange surface; and

sealing the front of the protective structure to protect the chip against environmental contamination, wherein the terminals are exposed at the front of the protective structure and are independently displaceable in said rearward direction towards the front side of the protective structure.

9. The method as claimed in claim 8, wherein the first film includes a bond window being juxtaposed with the chip in the placing step.

10. The method as claimed in claim 9, further comprising the steps of:

providing a support structure within the bond window with a space between the first film and the support structure defining a bond gap;

providing a plurality of first conductive leads on the first film, each first lead extending from one terminal to the support structure across the bond gap;

providing holding straps between the first film and the support structure so that the support structure is juxtaposed with the chip;

separating the first leads at a detachment point in proximity to the bonding gap and bonding each lead to a contact on the chip; and

removing the holding straps and the support structure subsequent to the bonding step.

11. The method as claimed in claim 9, further comprising the steps of:

providing a second flexible dielectric circuit film within the bond window and lying in a common plane with the first film with a space between the films defining a bond gap, the second film having conductive pads thereon, each pad being electrically connected to one contact on the chip; and

disposing compliant material between the second film and the front surface of the chip, wherein the pads are exposed at the front of the protective structure and are independently displaceable towards the front side of the protective structure.

12. The method as claimed in claim 11, the steps of providing first and second films further comprising the steps of:

providing a plurality of first conductive leads on the first film, each first lead extending from one terminal to the second film across the bond gap;

providing a plurality of second conductive leads on the second film, each second lead extending from one pad to the first film across the bond gap;

separating the first and second leads within or near the perimeter of the bonding gap; and

bonding each lead to one contact on the chip.

13. The method as claimed in claim 12, wherein the steps of providing first and second films further comprising the steps of:

providing holding straps between the first and second films prior to the separating step; and

removing the holding straps subsequent to the bonding step.

14. The method as claimed in claim 11, wherein the first and second films have a first surface facing away from the compliant material and a second surface facing toward the compliant material, and wherein the step of sealing includes providing a dielectric mask layer extending across the first surfaces of the films.

15. The method as claimed in claim 14, wherein the separating step includes separating each lead at a detachment point.

16. The method as claimed in claim 15, wherein the sealing step further includes disposing a compliant material within the indentation of the protective structure substantially encapsulating the chip therein.