Semiconductor wafer test and burn-in

• US 5,929,651 A
• Filed: 11/18/1996
• Issued: 07/27/1999
• Est. Priority Date: 08/09/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Walker, George Frederick, Leas, James Marc, Perry, Charles Hampton, Gardell, David Lewis, Prilik, Ronald, Koss, Robert William, Van Horn, Jody John, Dingle, Steve Leo
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US08/751,574
• Time in Patent Office: 981 Days
• Field of Search: 324/754, 324/72.5, 324/755, 324/758, 324/765, 324/760, 324/763
• US Class Current: 324/754.16
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Claims

1. An apparatus for simultaneously contacting a plurality of integrated circuit product chips having signal I/O, ground, and power pads, the product chips on a product water having a front surface and a back surface, the apparatus connectable to a power supply, the apparatus comprising:

a test head connectable to a plurality of the product chips on the product wafer, said test head comprising at least one test chip electrically connectable to the product chips, said at least one test chip having a front and a back surface; and

a plurality of voltage regulators on said at least one test chip, said regulators connectable between the power supply and the power pads on the product chips, wherein said regulators control the magnitude of the voltage and make the voltage delivered to each product chip under test conditions insensitive to the presence of shorted chips on the wafer and insensitive to the magnitude of the current drawn by each chip.

2. The apparatus as recited in claim 1, wherein said voltage regulators include at least one voltage regulator for each product chip.

3. The apparatus as recited in claim 2, further comprising electronic means for limiting current to each product chip if it has a short.

4. The apparatus as recited in claim 3, wherein said means to limit current comprises a gate control to said voltage regulators to disconnect power from selected product chips.

5. The apparatus as recited in claim 4, wherein said gate control has an externally controllable on state and off state.

6. The apparatus as recited in claim 3, wherein said means to limit current comprises a compliance current setting for each said voltage regulators.

7. The apparatus as recited in claim 6, wherein said compliance current setting is externally controllable.

8. The apparatus as recited in claim 2, further comprising a decoupling capacitor on an output line of each of said voltage regulators.

9. The apparatus as recited in claim 8, wherein said decoupling capacitor comprises one of a trench capacitor and a thin film capacitor.

10. The apparatus as recited in claim 8, wherein said decoupling capacitor is provided on each power pad of said carrier.

11. The apparatus as recited in claim 2, further comprising a sense line extending from said voltage regulators to the product chips to feed one of the Vdd voltages and the ground voltages on the product chips back to said voltage regulators.

12. The apparatus as recited in claim 1, wherein said test chip further comprises test circuits for testing the product chips.

13. The apparatus as recited in claim 1, comprising a plurality of said test chips, each said test chip separately mounted on a carrier.

14. The apparatus as recited in claim 13, further comprising a test chip corresponding to each product chip.

15. The apparatus as recited in claim 1, wherein the power supply provides a power voltage level and a ground voltage level, said power voltage level being supplied to said voltage regulators through said back surface of said test chips.

16. The apparatus as recited in claim 1, wherein said power supply provides a power voltage level and a ground voltage level, said ground voltage level being supplied through the back surface of the product chips.

17. The apparatus as recited in claim 1, said test chip further comprising means for disconnecting contact to the signal I/O pad of a product chip.

18. The apparatus as recited in claim 1, said test head further comprising power and ground metallization layers extending to opposite surfaces of said test head, said test head further comprising power bus and ground bus tabs connected to said power and ground metallization layers.

19. The apparatus as recited in claim 1, wherein said apparatus is capable of simultaneously contacting substantially all of the integrated circuit product chips on a product wafer.

20. The apparatus as recited in claim 1, wherein said test head has a contactor for contacting said power pads, said test head further comprising power distribution wiring for distributing power from the power supply to said contactor, said test head comprising a material having a thermal coefficient of expansion matching that of the product wafer.

21. The apparatus as recited in claim 20, wherein said test head material comprises a semiconductor, a ceramic material, a metal, or a laminated metal.

22. The apparatus as recited in claim 21, wherein said material comprises silicon, glass ceramic, aluminum nitride, Kovar, Invar, tungsten or molybdenum.

23. The apparatus as recited in claim 1, wherein said test head is a carrier for said test chip.

24. The apparatus as recited in claim 23, wherein the product wafer and said at least one test chip are mounted on opposite sides of said carrier, electrical connection between the product chips and said at least one test chip being provided through said carrier.

25. The apparatus as recited in claim 23, wherein power from the power supply is distributed to said test chip through said carrier.

26. The apparatus as recited in claim 23, wherein electrical connection between the product chips and said test chip is provided through said carrier.

27. The apparatus as recited in claim 23, wherein said carrier further comprises a contactor for contacting I/O pads on a plurality of the product chips on the product wafer said test chip comprising means for disconnecting contact to the signal I/O pads of a product chip.

28. The apparatus as recited in claim 1, wherein said test head comprises probes and a vacuum clamp for impelling said probes into contact with the product wafer.

29. The apparatus as recited in claim 28, wherein said vacuum clamp is designed to provide a vacuum seal to the back surface of the product wafer or the back surface of the test head.

30. The apparatus as recited in claim 29, wherein the product wafer has an edge, said vacuum seal being located near said edge.

31. The apparatus as recited in claim 29, wherein said vacuum seal rings the back surface of the product wafer, there being an outermost probe to the product wafer, said vacuum seal being located near said outermost probe.

32. The apparatus as recited in claim 28, said test bead further comprising a latch for assuring alignment of the product wafer if said vacuum clamp fails.

33. The apparatus as recited in claim 28, wherein said clamp allows moving the apparatus after clamping to the product wafer.

34. A apparatus as recited in claim 1, wherein said test head further comprises connectors for external connection.

35. The apparatus as recited in claim 34, wherein said test head further comprises a plurality of connectors for connecting said test head to a tester.

36. A apparatus as recited in claim 34, wherein said test head provides an external reference voltage to one said voltage regulator on an externally accessible reference signal line, wherein said regulator provides said power from said power supply to a power pad of a product chip at a voltage level corresponding to that applied on an said reference signal line.

37. A apparatus as recited in claim 36, wherein said voltage regulator further comprises means for sensing the voltage difference on the product chips on the wafer and correspondingly adjusting the output voltage of said voltage regulator so that the voltage difference matches the reference voltage.

38. The apparatus as recited in claim 1, further comprising means for providing a plurality of voltage levels simultaneously.

39. The apparatus as recited in claim 1, wherein the product wafer has a back surface, further comprising an array of pistons capable of contacting most of the area of the back surface of the wafer, and means for providing force to each piston of said array capable of providing thermal contact between said piston and the wafer to control the temperature of the wafer.

40. The apparatus as recited in claim 39, wherein said means for providing force provides force capable of impelling the wafer toward said test head to achieve electrical contact to all portions of the wafer.

41. The apparatus as recited in claim 1, said test head further comprising power and ground metallization layers extending to opposite surfaces of said test head, said test head further comprising power bus and ground bus tabs connected to said power and ground metallization layers.