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Semiconductor wafer test and burn-in

  • US 5,929,651 A
  • Filed: 11/18/1996
  • Issued: 07/27/1999
  • Est. Priority Date: 08/09/1995
  • Status: Expired due to Fees
First Claim
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1. An apparatus for simultaneously contacting a plurality of integrated circuit product chips having signal I/O, ground, and power pads, the product chips on a product water having a front surface and a back surface, the apparatus connectable to a power supply, the apparatus comprising:

  • a test head connectable to a plurality of the product chips on the product wafer, said test head comprising at least one test chip electrically connectable to the product chips, said at least one test chip having a front and a back surface; and

    a plurality of voltage regulators on said at least one test chip, said regulators connectable between the power supply and the power pads on the product chips, wherein said regulators control the magnitude of the voltage and make the voltage delivered to each product chip under test conditions insensitive to the presence of shorted chips on the wafer and insensitive to the magnitude of the current drawn by each chip.

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