Memory interface circuit and access method

• US 5,929,832 A
• Filed: 03/01/1996
• Issued: 07/27/1999
• Est. Priority Date: 03/28/1995
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Furukawa, Hiroyuki, Yamamoto, Kunihiko
• Primary Examiner(s): WU, XIAO MIN
• Application Number:
  US08/609,475
• Time in Patent Office: 1,243 Days
• Field of Search: 345/94, 345/100, 345/103, 345/185, 345/98, 345/99, 345/87, 345/208, 345/213, 345/507
• US Class Current: 345/98
• CPC Class Codes: G09G 3/3625 using active addressing

Abstract

The memory interface circuit converts an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display. The memory interface circuit includes: a memory for storing one frame of the input data signal corresponding to the display panel, and a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner. The control circuit controls timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after that for the first multi-scan signal is started, the predetermined time being equal to a delay time of a write operation of the input data corresponding to the second portion with respect to that corresponding to the first portion.

Claims

1. A memory interface circuit for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion and a second portion, the memory interface circuit including:

a memory for receiving and storing one frame of the input data signal corresponding to the display panel, and

a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel,

wherein the control circuit controls the timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after a read operation for the first multi-scan signal is started and before the read operation of the first multi-scan signal is completed, the predetermined time being equal to a delay time of a start of a write operation of the input data signal corresponding to the second portion with respect to a start of a write operation of the input data signal corresponding to the first portion.

2. A memory interface circuit according to claim 1,

wherein the display panel includes a plurality of display blocks each having a plurality of scanning lines, and the liquid crystal display performs an orthogonal transform on the input video signal by the display block and simultaneously selects the plurality of scanning lines by the display block, and

wherein the memory means includes a plurality of memory blocks each corresponding to respective one of the display blocks, and the memory means has a memory capacity for storing one frame of the input data signal.

3. A memory interface circuit according to claim 2, wherein the control circuit includes:

a write/read decision circuit for deciding for which memory block a write operation should be performed, and for outputting a decision signal for directing read/write operations for the memory blocks; and

an address generator for generating a first address signal for write operations and a second address signal for read operations,

whereby the input data signal is sequentially written in the plurality of the memory blocks according to the decision signal and the first address signal, and the data stored in one memory block is simultaneously read out for the corresponding display block according to the decision signal and the second address signal.

4. A memory interface circuit according to claim 3, wherein the data stored in the plurality of memory blocks is sequentially read out by the memory block for each of the first and second portions.

5. A memory interface circuit according to claim 3,

wherein the write/read decision circuit makes a decision according to a first horizontal synchronizing signal which is included in the input data signal, and

wherein the address generator generates the first address signal based on the first horizontal synchronizing signal, and generates the second address signal based on a given second horizontal synchronizing signal.

6. A memory interface circuit according to claim 2, wherein the control circuit controls timing of read and write operations so that the input data signal is written in and read out from each memory block respectively once a frame period, the frame period corresponding to one frame of the input data signal.

7. A memory interface circuit according to claim 2, wherein the control circuit controls timing of read and write operations so that the input data is written in each memory block once a frame period, and that the data stored in each memory block is read out twice a frame period, the frame period corresponding to one frame of the input data signal.

8. A memory interface circuit according to claim 1, wherein the control circuit further controls the timing of write operations so that a write operation of the input data corresponding to the first portion for one frame is started before a completion of the read operation for the second multi-scan signal for the second portion for the previous frame.

9. A memory interface circuit according to claim 8, wherein the memory includes a plurality of memory blocks, and wherein the write operation of the input data corresponding to the first portion for one frame is started before a completion of the read operation for the first multi-scan signal for the first portion for the previous frame, and the write operation of the input data corresponding to the second portion for said one frame is started before a completion of the read operation for the second multi-scan signal for the second portion for the previous frame.

10. A method for controlling access operations of a memory used for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion and a second portion, the memory storing one frame of the input data signal corresponding to the display panel, the method including the steps of:

(a) sequentially performing write operations of the input data signal for the memory in a single-scan manner; and

(b) performing read operations for the memory whereby first and second multi-scan signals are read out in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel,

wherein step (b) includes the steps of;

(b1) reading the data for the first multi-scan signal from the memory; and

(b2) reading the data for the second multi-scan signal from the memory a predetermined time after a beginning of step (b1) and before a completion of step (b1), the predetermined time being equal to a delay time of a beginning of the write operation of the input data signal corresponding to the second portion with respect to a beginning of the write operation of the input data signal corresponding to the first portion, the write operations being performed in step (a).

11. A method for controlling access operations of the memory according to claim 10,

wherein the display panel includes a plurality of display blocks each having a plurality of scanning lines, and the liquid crystal display performs an orthogonal transform on the input video signal by the display block and simultaneously selects the plurality of scanning lines by the display block, and the memory includes a plurality of memory blocks each corresponding to respective one of the display blocks, a memory capacity of the memory being a right amount for storing one frame of the input data,

the method including the steps of:

(c) deciding for which memory block a write operation should be performed;

(d) generating a decision signal indicating the result of step (c);

(e) generating a first address signal for write operations and a second address signal for read operations;

(f) performing write operations according to the decision signal and the first address signal so that the input data signal is sequentially written in the plurality of the memory blocks; and

(g) performing read operations according to the decision signal and the second address signal so that the data stored in one memory block is simultaneously read out for the corresponding display block, and that the data stored in the memory blocks is sequentially read out by the memory block for each of the first and second portions.

12. A method for controlling access operations of the memory according to claim 11, wherein

in step (c), a decision is made according to a first horizontal synchronizing signal included in the input data signal, and

in step (e), the first address signal is generated based on the first horizontal synchronizing signal and the second address signal is generated based on a given second horizontal synchronizing signal.

13. A method for controlling access operations of the memory according to claim 11,

wherein step (f) includes the steps of:

(f1) setting one memory block of the memory means in a write mode so as to write the input data therein based on the decision signal; and

(f2) setting the other memory blocks in a read mode based on the decision signal, and

wherein step (g) includes the steps of;

(g1) selecting a memory block corresponding to the first portion and another memory block corresponding to the second portion from the other memory blocks in the read mode based on the first horizontal synchronizing signal;

(g2) setting the selected memory blocks in a read enable state so as to read the data therefrom; and

(g3) setting non-selected memory blocks in a read-prohibit state to prevent read operation therefor.

14. A method for controlling access operations of the memory according to claim 11, wherein the input data signal is written in and read out from each memory block respectively once a frame period, the frame period corresponding to one frame of the input data signal.

15. A method for controlling access operations of the memory according to claim 11, wherein the input data signal is written in each memory block once a frame period, and the data stored in each memory block is read out twice a frame period, the frame period corresponding to one frame of the input data signal.

16. A method for controlling access operations of the memory according to claim 10, wherein the step (a) is performed so that a write operation of the input data signal corresponding to the first portion for one frame is started before a completion of the read operation for the second multi-scan signal for the second portion for the previous frame.

17. A method for controlling access operations of the memory according to claim 16, wherein the memory includes a plurality of memory blocks, and wherein the write operation of the input data corresponding to the first portion for one frame is started before a completion of the read operation for the first multi-scan signal for the first portion for the previous frame, and the write operation of the input data corresponding to the second portion for said one frame is started before a completion of the read operation for the second multi-scan signal for the second portion for the previous frame.

18. A memory interface circuit for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion having a plurality of scanning signal lines and a second portion having a plurality of scanning signal lines, the memory interface circuit including:

a memory for receiving and storing one frame of the input data signal corresponding to the display panel, and

a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel,

wherein at least two lines of the scanning signal lines of the first portion are selected simultaneously, and each of the at least two lines of the scanning signal lines of the first portion is supplied with a plurality of selection pulses per frame and

at least two lines of the scanning signal lines of the second portion are selected simultaneously, and each of the at least two lines of the scanning signal lines of the second portion is supplied with a plurality of selection pulses per frame.

19. A memory interface circuit according to claim 18, wherein the at least two lines of the scanning signal lines of the first and second portions are selected simultaneously using a non-dispersion type MLS method.