Memory interface circuit and access method
First Claim
1. A memory interface circuit for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion and a second portion, the memory interface circuit including:
- a memory for receiving and storing one frame of the input data signal corresponding to the display panel, anda control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel,wherein the control circuit controls the timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after a read operation for the first multi-scan signal is started and before the read operation of the first multi-scan signal is completed, the predetermined time being equal to a delay time of a start of a write operation of the input data signal corresponding to the second portion with respect to a start of a write operation of the input data signal corresponding to the first portion.
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Accused Products
Abstract
The memory interface circuit converts an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display. The memory interface circuit includes: a memory for storing one frame of the input data signal corresponding to the display panel, and a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner. The control circuit controls timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after that for the first multi-scan signal is started, the predetermined time being equal to a delay time of a write operation of the input data corresponding to the second portion with respect to that corresponding to the first portion.
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Citations
19 Claims
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1. A memory interface circuit for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion and a second portion, the memory interface circuit including:
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a memory for receiving and storing one frame of the input data signal corresponding to the display panel, and a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel, wherein the control circuit controls the timing of read operations so that a read operation for the second multi-scan signal is started a predetermined time after a read operation for the first multi-scan signal is started and before the read operation of the first multi-scan signal is completed, the predetermined time being equal to a delay time of a start of a write operation of the input data signal corresponding to the second portion with respect to a start of a write operation of the input data signal corresponding to the first portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for controlling access operations of a memory used for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion and a second portion, the memory storing one frame of the input data signal corresponding to the display panel, the method including the steps of:
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(a) sequentially performing write operations of the input data signal for the memory in a single-scan manner; and (b) performing read operations for the memory whereby first and second multi-scan signals are read out in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel, wherein step (b) includes the steps of; (b1) reading the data for the first multi-scan signal from the memory; and (b2) reading the data for the second multi-scan signal from the memory a predetermined time after a beginning of step (b1) and before a completion of step (b1), the predetermined time being equal to a delay time of a beginning of the write operation of the input data signal corresponding to the second portion with respect to a beginning of the write operation of the input data signal corresponding to the first portion, the write operations being performed in step (a). - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A memory interface circuit for converting an input data signal into multi-scan data signals used for a multi-scan type liquid crystal display including a display panel comprising a first portion having a plurality of scanning signal lines and a second portion having a plurality of scanning signal lines, the memory interface circuit including:
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a memory for receiving and storing one frame of the input data signal corresponding to the display panel, and a control circuit for controlling write/read operations for the memory so that the input data signal is sequentially written in the memory in a single-scan manner, and that data stored in the memory is read out as first and second multi-scan signals in a multi-scan manner, the first multi-scan signal corresponding to the first portion of the display panel and the second multi-scan signal corresponding to the second portion of the display panel, wherein at least two lines of the scanning signal lines of the first portion are selected simultaneously, and each of the at least two lines of the scanning signal lines of the first portion is supplied with a plurality of selection pulses per frame and at least two lines of the scanning signal lines of the second portion are selected simultaneously, and each of the at least two lines of the scanning signal lines of the second portion is supplied with a plurality of selection pulses per frame. - View Dependent Claims (19)
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Specification