Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques

• US 5,930,148 A
• Filed: 12/16/1996
• Issued: 07/27/1999
• Est. Priority Date: 12/16/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schmookler, Martin S., Bjorksten, Andrew A., Zoric, Brian A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US08/767,407
• Time in Patent Office: 953 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

Claims

1. A method of verifying a digital circuit design, said method comprising:

providing a digital circuit design including a plurality of circuit cells, said plurality of circuit cells including a first circuit cell and a second circuit cell that utilize diverse circuit techniques, said first circuit cell including dynamic logic, wherein an input of said first circuit cell is connected to an output of said second circuit cell;

defining a first set of timing constraints for said first circuit cell, wherein each timing constraint within said first set of timing constraints prevents a possible mode of failure of said first circuit cell; and

verifying said digital circuit design, wherein said verification includes a determination of whether or not said first circuit cell satisfies said first set of timing constraints while connected to said second circuit cell.

2. The method of claim 1, wherein, said step of providing a digital circuit design comprises:

providing a library of compatible circuit cells;

in response to receipt of a description of said digital circuit design, automatically synthesizing said plurality of circuit cells within said digital circuit design, wherein at least one circuit cell among said plurality of circuit cells within said digital circuit design is selected from within said library; and

connecting each of said plurality of circuit cells to at least one other circuit cell among said plurality of circuit cells.

3. The method of claim 2, wherein each of said plurality of circuit cells is connected individually, and wherein said verifying step is performed after each of said plurality of circuit cells is connected.

4. The method of claim 1, wherein said first circuit cell performs a particular logical function, said method further comprising:

in response to a determination that said first circuit cell fails to satisfy said first set of timing constraints, replacing said first circuit cell with a third circuit cell that performs said particular logical function utilizing a diverse circuit technique.

5. The method of claim 1, wherein:

said digital circuit design has a plurality of clock signals, wherein first and second clock signals among said plurality of clock signals have identical periods and said second clock signal is delayed with respect to said first clock signal;

said verifying step comprises the step of determining if said first circuit cell satisfies said first set of timing constraints when clocked by said first clock signal; and

said method further comprises the step of;

in response to a determination that said first circuit cell fails to satisfy said first set of timing constraints when clocked by said first clock signal, repeating said verifying step while clocking said first circuit cell with said second clock signal.

6. The method of claim 1, and further comprising the step of:

repeating said verifying step in response to placement of said plurality of circuit cells in a selected physical arrangement.

7. The method of claim 1, wherein said plurality of circuit cells includes a static circuit cell, wherein said verifying step further comprises the step of verifying that an output signal of said static circuit cell has a correct signal inversion relationship with an input signal of said static circuit cell.

8. A system for digital circuit design, said system comprising:

a processing unit;

a memory coupled to said processing unit;

a first set of timing constraints stored within said memory, wherein said first set of timing constraints is associated with a first dynamic circuit technique, wherein each timing constraint within said first set of timing constraints prevents a possible mode of failure of circuit cells of said first dynamic circuit technique; and

a timing verification program stored within said memory and executable by said processing unit, wherein in response to receipt of a digital circuit design comprising a first circuit cell utilizing said first dynamic circuit technique and a second circuit cell utilizing a diverse circuit technique, said first circuit cell having an input connected to an output of said second circuit cell, said timing verification program verifies said digital circuit design, wherein said timing verification program includes means for determining whether said first circuit cell satisfies said first set of timing constraints while connected to said second circuit cell.

9. The system of claim 8, said system further comprising:

a logic synthesis program stored within said memory and executable by said processing unit, wherein in response to receipt of a functional description of said digital circuit design, said functional description indicating a plurality of logical functions, said logic synthesis program synthesizes a plurality of circuit cells that implement said plurality of logical functions and connects each of said plurality of circuit cells to at least one other circuit cell; and

a library accessible by said logic synthesis program, wherein said library includes a plurality of predetermined circuit cells.

10. The system of claim 9, and further comprising:

means for creating said functional description of said digital circuit design.

11. The system of claim 9, wherein said logic synthesis program connects each of said plurality of circuit cells individually, and wherein said timing verification program verifies said digital circuit design after each of said plurality of circuit cells is connected.

12. The system of claim 9, wherein said first circuit cell performs a particular logical function, said logic synthesis program further comprising:

means, responsive to a determination by said timing verification program that said first circuit cell fails to satisfy said first set of timing constraints, for replacing said first circuit cell with a third circuit cell that performs said particular logical function utilizing a diverse dynamic circuit technique.

13. The system of claim 8, wherein:

said digital circuit design has a plurality of clock signals, wherein first and second clock signals among said plurality of clock signals have identical periods and said second clock signal is delayed with respect to said first clock signal; and

said timing verification program further comprises;

means, responsive to a determination that said first circuit cell fails to satisfy said first set of timing constraints when clocked by said first clock signal, for repeating said verifying step while clocking said first circuit cell with said second clock signal.

14. The system of claim 8, wherein:

said system further comprises means for automatically placing said plurality of circuit cells comprising said digital circuit design in a physical arrangement; and

said timing verification program includes means for verifying said digital circuit design in response to placement of said plurality of circuit cells in said physical arrangement.

15. The system of claim 8, wherein said digital circuit design includes a static circuit cell having an input for receiving an input signal and an output for outputting an output signal, wherein said timing verification program further comprises means for verifying that said output signal has a correct signal inversion relationship with said input signal.

16. A program product for use with a data processing system, said program product comprising:

a first set of timing constraints associated with a first dynamic circuit technique, wherein each timing constraint within said first set of timing constraints prevents a possible mode of failure of circuit cells of said first dynamic circuit technique; and

a timing verification program executable a data processing system, wherein in response to receipt of a digital circuit design comprising a first circuit cell utilizing said first dynamic circuit technique and a second circuit cell utilizing a diverse circuit technique, said first circuit cell having an input connected to ii an output of said second circuit cell, said timing verification program verifies said digital circuit design, wherein said timing verification program includes means for determining whether said first circuit cell satisfies said first set of timing constraints while connected to said second circuit cell; and

signal-bearing media bearing said first set of timing constraints and said timing verification program.

17. The program product of claim 16, said program product further comprising:

a logic synthesis program executable by said data processing system, wherein in response to receipt of a functional description of said digital circuit design, said functional description indicating a plurality of logical functions, said logic synthesis program synthesizes a plurality of circuit cells that implement said plurality of logical functions and connects each of said plurality of circuit cells to at least one other circuit cell; and

a library accessible by said logic synthesis program, wherein said library includes a plurality of predetermined circuit cells.

18. The program product of claim 17, and further comprising:

means for creating said functional description of said digital circuit design.

19. The program product of claim 17, wherein said logic synthesis program connects each of said plurality of circuit cells individually, and wherein said timing verification program verifies said digital circuit design after each of said plurality of circuit cells is connected.

20. The program product of claim 17, wherein said first circuit cell performs a particular logical function, said logic synthesis program further comprising:

means, responsive to a determination by said timing verification program that said first circuit cell fails to satisfy said first set of timing constraints, for replacing said first circuit cell with a third circuit cell that performs said particular logical function utilizing a diverse dynamic circuit technique.

21. The program product of claim 16, wherein:

said digital circuit design has a plurality of clock signals, wherein first and second clock signals among said plurality of clock signals have identical periods and said second clock signal is delayed with respect to said first clock signal; and

said timing verification program further comprises;

means, responsive to a determination that said first circuit cell fails to satisfy said first set of timing constraints when clocked by said first clock signal, for repeating said verifying step while clocking said first circuit cell with said second clock signal.

22. The program product of claim 16, wherein:

said program product further comprises means for automatically placing said plurality of circuit cells comprising said digital circuit design in a physical arrangement; and

said timing verification program includes means for verifying said digital circuit design in response to placement of said plurality of circuit cells in said physical arrangement.

23. The program product of claim 16, wherein said digital circuit design includes a static circuit cell having an input for receiving an input signal and an output for outputting an output signal, wherein said timing verification program further comprises means for verifying that said output signal has a correct signal inversion relationship with said input signal.