Semiconductor memory device having two P-well layout structure

• US 5,930,163 A
• Filed: 12/18/1997
• Issued: 07/27/1999
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Hiroyuki, Matsui, Masataka
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US08/993,180
• Time in Patent Office: 586 Days
• Field of Search: 365/154, 365/156, 257/903, 257/904
• US Class Current: 365/154
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.

Claims

1. A semiconductor memory device comprising:

a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor;

a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor, and having an input terminal connected to an output terminal of said first inverter and an output terminal connected to an input terminal of said first inverter;

a third N-channel MOS transistor having a source connected to the output terminal of said first inverter, a drain connected to a first bit line, and a gate connected to a word line; and

a fourth N-channel MOS transistor having a source connected to an output terminal of said second inverter, a drain connected to a second bit line, and a gate connected to said word line,

wherein a layout direction of a source and drain of each of said first, second, third, and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is set parallel to a boundary between a P-well region where said first, second, third, and fourth N-channel MOS transistors are formed, and an N-well region where said first and second P-channel MOS transistors are formed.

2. A device according to claim 1, wherein the layout direction of the source and drain of each of said first, second, third, and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is set parallel to said bit line.

3. A device according to claim 1, wherein the P-well region is made up of first and second well regions, and the first and second P-well regions are laid out on both sides of the N-well region where said first and second P-channel MOS transistors are arranged, and

said first and third N-channel MOS transistors are formed in the first P-well region, and said second and fourth N-channel MOS transistors are formed in the second P-well region.

4. A device according to claim 3, wherein the layout direction of the source and drain of each of said first, second, third, and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is set parallel to said bit line.

5. A device according to claim 4, wherein a first polysilicon wiring layer used for the gate of said third N-channel MOS transistor, and a second polysilicon wiring layer used for gates of said first N-channel MOS transistor and said first P-channel MOS transistor are laid out parallel to each other,

a third polysilicon wiring layer used for the gate of said fourth N-channel MOS transistor, and a fourth polysilicon wiring layer used for gates of said second N-channel MOS transistor and said second P-channel MOS transistor are laid out parallel to each other, and

said first and third polysilicon wiring layers are formed to be isolated from each other, and electrically connected via contacts to a metal wiring layer constituting said word line.

6. A device according to claim 5, wherein the layout direction of the source and drain of each of said first, second, third, and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is set parallel to said bit line.

7. A device according to claim 5, wherein said second and third polysilicon wiring layers are laid out to align on one straight line along a direction of said word line, and

said first and fourth polysilicon wiring layers are laid out to align on one straight line along a direction of said word line.

8. A device according to claim 7, wherein said first and third N-channel MOS transistors are formed in the same diffusion layer within the first P-well region, and

said second and fourth N-channel MOS transistors are formed in the same diffusion layer within the second P-well region.

9. A device according to claim 8, wherein said first and third N-channel MOS transistors and said first P-channel MOS transistor, and said second and fourth N-channel MOS transistors and said first P-channel MOS transistor are laid out to be point-symmetrical about a center of a memory cell.

10. A device according to claim 9, wherein said first and second bit lines, and a power supply line connected to the sources of said first and second P-channel MOS transistors are made of second metal wiring layers, and

said word line, and a ground line connected to the sources of said first and second N-channel MOS transistors are made of third metal wiring layers.

11. A device according to claim 10, wherein said first polysilicon wiring layer used for the gate of said third N-channel MOS transistor, and said second polysilicon wiring layer used for the gates of said first N-channel MOS transistor and said first P-channel MOS transistor are laid out parallel to each other,

said third polysilicon wiring layer used for the gate of said fourth N-channel MOS transistor, and said fourth polysilicon wiring layer used for the gates of said second N-channel MOS transistor and said second P-channel MOS transistor are laid out parallel to each other,

said word line is divisionally formed by first and second metal wiring layers, and

said first and third polysilicon wiring layers are formed to be isolated from each other, and electrically connected via a metal wiring layer and contacts to said first and second metal wiring layers.

12. A device according to claim 11, wherein first and second sense amplifiers are independently connected to said first and second bit lines,

in a write, first and second word lines within the same cell are simultaneously selected, and

in a read, said first and second word lines independently select different cells, and data read from the cells are output from said first and second sense amplifiers via said first and second bit lines.

13. A semiconductor memory device comprising:

a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor;

a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor, and having an input terminal connected to an output terminal of said first inverter and an output terminal connected to an input terminal of said first inverter;

a third P-channel MOS transistor having a drain connected to the output terminal of said first inverter, a source connected to a first bit line, and a gate connected to a word line; and

a fourth P-channel MOS transistor having a drain connected to an output terminal of said second inverter, a source connected to a second bit line, and a gate connected to said word line,

wherein a layout direction of a source and drain of each of said first and second N-channel MOS transistors and said first, second, third, and fourth P-channel MOS transistors is set parallel to a boundary between a P-well region where said first and second N-channel MOS transistors are formed, and an N-well region where said first, second, third, and fourth P-channel MOS transistors are formed.