Multi-state non-volatile flash memory capable of being its own two state write cache

• US 5,930,167 A
• Filed: 07/30/1997
• Issued: 07/27/1999
• Est. Priority Date: 07/30/1997
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lee, Douglas J., Chen, Jian
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/902,776
• Time in Patent Office: 727 Days
• Field of Search: 365/185.03, 365/185.24, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

A memory system including an array of flash EEPROM cells arranged in blocks of cells that are erasable together, with individual cells storing more than one bit of data as a result of operating the individual cells with more than two detectable threshold ranges or states. Any portion of the array in which data is not stored can be used as a write cache, where individual ones of the cells store a single bit of data by operating with only two detectable threshold ranges. Data coming into the memory is initially written in available blocks in two states since writing in more than two states takes significantly more time. At a later time, in the background, the cached data is read, compressed and written back into fewer blocks of the memory in multi-state for longer term storage at a reduced cost.

Claims

1. A non-volatile data memory, comprising:

an array of flash EEPROM cells organized into blocks of cells that are individually erasable as a unit,

a decoder responsive to address signals to address specific cells within a block for a data transfer operation, and

a data register circuit operably connectable through the decoder to transfer data between the register and the addressed cells, said data register circuit being operable to perform said data transfer with a density of either a first or a second number of data bits per individual addressed cell in response to a control signal, said data register circuit additionally being capable of reading data from the array at the first data bit density and writing the read data back into the array at the second data bit density.

2. The memory of claim 1, wherein the data register circuit further includes a number of register stages per addressed cell equal to a higher of the first and second numbers of data bits per addressed cell, and wherein the data register circuit operates to store the data read from the array at the first data bit density in fewer than said number of register stages and then shift at least some of the read data bits into said number of register stages per addressed cell for writing the read data back into the array at the second data bit density.

3. The memory of either one of claims 1 or 2, wherein said first data bit density is one bit per cell and said second data bit density is more than one bit per cell.

4. A method of operating a memory system of flash EEPROM cells, comprising:

writing a file of incoming data into the system with a first set of memory cell threshold voltage levels,

thereafter, reading said data file from the system, and

rewriting the read data file into the system with a second set of memory cell threshold voltage levels different from said first set, wherein the second set of memory cell threshold voltage levels include higher margin voltages within threshold voltage ranges than the first set of memory cell threshold voltage levels.

5. The method according to claim 4, wherein the second set of memory cell threshold voltage levels additionally includes a higher number of threshold voltage ranges than the first set of memory cell threshold voltage levels.

6. The method according to either of claims 4 or 5, including performing the method on flash EEPROM cells formed on a single integrated circuit chip.

7. The method according to either of claims 4 or 5, including performing the method on flash EEPROM cells formed on two or more integrated circuit chips.

8. A method of operating a flash EEPROM cell array, comprising:

caching a file of incoming data into a given number of cells of the array according to an amount of data within the file,

thereafter, reading said data file from the array,

compressing the read data file by applying a compression algorithm to the read data file that translates the data file into a compressed file, and

writing the compressed data file into a significantly fewer number of cells of the array than said given number.

9. A method of operating a flash EEPROM cell array on one or more integrated circuit chips, comprising:

operating individual cells of at least a portion of the array with either a first number of storage states or a second number of storage states higher than the first number,

writing an incoming data file into cells of said at least a portion of the array in the first storage state,

thereafter, reading said data file from the array, and

rewriting the read data file into said at least a portion of the memory in the second state, thereby to compress storage of the data file into fewer cells of the array, wherein the reading and rewriting of the data file occurs in response to the memory array becoming full with data.

10. The method of claim 9, which additionally includes either writing a second incoming data file into cells of said at least a portion of the array or reading a third data file already stored within the array cells simultaneously with said reading and rewriting of the data file.

11. The method of claim 9, wherein the writing and rewriting operations include both using at least some of the same array cells.

12. The method of claim 9, wherein operating the individual cells includes doing so with a third number of storage states higher than the second number, and additionally comprising, in response to the memory array becoming full with data:

again reading said data file from the array, and

rewriting the read data file into said at least a portion of the memory in the third state, thereby to further compress storage of the data file in the array.

13. The method of any one of claims 9-12 wherein the first number is two and the second number is greater than two.

14. The method of claim 13, wherein the second number is four.

15. The method of any one of claims 9-12, wherein the rewriting of the data file includes rewriting said data file into cells of said at least a portion of the array that are different from the cells in which the incoming data file was written in the first storage state.

16. A method of operating a memory system of flash EEPROM cells organized into blocks of cells that are erasable together, wherein the individual cells are operable in any of at least a first data density level of two storage states and a second data density level of more than two storage states, comprising:

initially writing data into blocks of cells at the first density level,

determining when a threshold proportion of the memory system blocks are filled with data written into the blocks with the first density level,

thereafter compressing data already stored in the memory in the first density level by reading said stored data at the first density level from a first number of blocks of cells and rewriting the read data at the second density level into a second number of blocks of cells less than the first number of blocks of cells, thereby to make a number of blocks of cells equal to a difference between said first and second numbers of blocks available to store additional data, and

thereafter storing additional data in at least some of the number of blocks made available by the data compression.

17. The method of claim 16, wherein the additional data is initially stored at the first density level in at least some of the number of blocks made available by the data compression.

18. The method of claim 16, additionally comprising thereafter compressing data already stored in the memory in the second density level by reading said stored data at the second density level from the second number of blocks of cells and rewriting the read data at a third density level into a third number of blocks of cells less than the second number of blocks of cells, thereby to make a number of blocks of cells equal to a difference between said second and third numbers of blocks available to store further additional data.

19. The method of claim 18, wherein the further additional data is initially stored at the first density level in at least some of the number of blocks made available by the data compression.

20. A method of operating a memory system of flash EEPROM cells organized into blocks of cells that are erasable together, wherein the individual cells are operable in any of at least a first data density level of two storage states and a second data density level of more than two storage states, comprising:

writing a file of incoming data into the memory system with a first set of memory cell threshold voltage levels,

thereafter, reading said data file from the memory system,

rewriting the read data file into the system with a second set of memory cell threshold voltage levels greater than that of said first set, and

maintaining separate counts for the blocks individually of the number of times that data has been written into the individual blocks with the first set of threshold voltage levels and the number of times with the second set of threshold voltage levels.

21. A method of operating a memory system of flash EEPROM cells that is alternatively powered from a battery or a power line source, comprising:

writing a file of incoming data into the memory system with a first set of memory cell threshold voltage levels when the memory system is powered from the battery, and

thereafter, when the memory system is powered from a power, line source, reading said data file from the memory system, and rewriting the read data file back into the memory system with a second set of memory cell threshold voltage levels that is higher than said first set.