Memory system using a flash memory and method of controlling the memory system

• US 5,930,193 A
• Filed: 12/29/1997
• Issued: 07/27/1999
• Est. Priority Date: 06/29/1994
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamamoto, Akira, Achiwa, Kyosuke, Yamagata, Hirotsugu
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/998,998
• Time in Patent Office: 575 Days
• Field of Search: 365/230.03, 365/230.04, 365/236, 365/185.33
• US Class Current: 365/230.03
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory system includes a flash memory having a plurality of individually erasable physical blocks, table section for holding the relationship in correspondence between the logical blocks allocated by the allocation section and the physical blocks first counting and managing section for counting and managing write counts of the respective logical blocks, first classifying section for classifying the logical blocks into a plurality of groups on the basis of the respective write counts of the logical blocks, erasure section for erasing data in a physical block allocated to a logical block to produce a free physical block, second counting and managing section for counting and managing the erasure counts of the respective physical blocks, second classifying section for classifying the physical blocks into a plurality of groups on the basis of the respective erasure counts of the physical blocks, control section for allocating the respective logical blocks to the physical blocks; and managing section for managing free physical blocks which are not allocated to any logical blocks.

Claims

1. A memory system coupled to a first CPU that issues write request to a logical block of said memory system, comprising:

a) a plurality of physical blocks; and

b) a second CPU, that counts a write count of each logical block, and allocates said each logical block to one of said plurality of physical blocks based on the counting result.

2. A memory system, comprising:

a) a plurality of physical blocks; and

b) a CPU, that

c) counts a write count of each logical block; and

d) allocates said each logical block to one of said plurality of physical blocks based on the counting result.