Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access

• US 5,930,484 A
• Filed: 09/18/1997
• Issued: 07/27/1999
• Est. Priority Date: 09/18/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kahle, James Allan, Tran, Cang Ngoc
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/933,156
• Time in Patent Office: 677 Days
• Field of Search: 395/309, 395/827, 395/840, 395/841, 395/287, 395/311, 395/306
• US Class Current: 710/107
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.

Claims

1. An input/output control method for a multiprocessor system having a plurality of processors and a common wide bus subdivided into a plurality of sub-buses, said method comprising the steps of:

matching a target device and one or more of said plurality of processors, in response to a transfer request by one or more of said plurality of processors;

simultaneously utilizing one or more of said plurality of sub-buses to transfer data to or from a particular processor among said plurality of processors in response to a transfer request from said particular processor; and

simultaneously utilizing one or more of said plurality of sub-buses to transfer data to or from each of multiple ones of said plurality of processors simultaneously in response to transfer requests by multiple ones of said plurality of processors.

2. The input/output control method according to claim 1, further including the step of associating an address for desired data with each transfer request.

3. The input/output control method according to claim 2, wherein multiprocessor system includes a plurality of target devices and wherein said method further includes the step of utilizing said address for desired data associated with each transfer request to identify a particular target device among said plurality of said target devices.

4. The input/output control method according to claim 3, further including the step of writing said address for desired data into an address queue.

5. The input/output control method according to claim 4, further including the step of delaying a transfer to or from one or more said plurality of processors in response to an indication that said address queue is full.

6. An input/output control system for a multiprocessor system having a plurality of processors and a common wide bus subdivided into a plurality of sub-buses, said system comprising:

means for matching a target device and one or more of said plurality of processors, in response to a transfer request by one or more of said plurality of processors;

means for simultaneously utilizing one or more of said plurality of sub-buses to transfer data to or from a particular processor among said plurality of processors in response to a transfer request from said particular processor; and

means for simultaneously utilizing one or more of said plurality of sub-buses to transfer data to or from each of multiple ones of said plurality of processors simultaneously in response to transfer requests by multiple ones of said plurality of processors.

7. The input/output control system according to claim 6, further including means for associating an address for desired data with each transfer request.

8. The input/output control system according to claim 6, wherein said multiprocessor system includes a plurality of target devices and wherein said system further includes means for utilizing said address for desired data associated with each transfer request to identify a particular target device among said plurality of target devices.

9. The input/output control system according to claim 8, wherein one of said plurality of target devices comprises a memory.

10. The input/output control system according to claim 8, wherein one of said plurality of target devices comprises a disk drive.

11. The input/output control system according to claim 8, wherein one of said plurality of target devices comprises a modem.