Stress migration evaluation method

• US 5,930,587 A
• Filed: 08/27/1997
• Issued: 07/27/1999
• Est. Priority Date: 08/27/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Ryan, Vivian W.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US08/917,955
• Time in Patent Office: 699 Days
• Field of Search: 438/14, 438/927, 438/FOR 468, 438/663, 438/799, 374/5, 374/57, 148/DIG. 3, 148/DIG. 90, 148/DIG. 162, 73/866
• US Class Current: 438/14
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311
• CPC Class Codes: Y10S 148/003 Anneal
• CPC Class Codes: Y10S 148/162 Testing steps
• CPC Class Codes: Y10S 438/927 Electromigration resistant metallization

Abstract

A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy. By analyzing the void size distribution data for the isothermal void propagation annealing, a measure of the long term reliability is provided.

Claims

1. A method for evaluating stress migration effects on a conductive runner fabricated according to a given fabrication process, said method comprising the steps of:

heating said runner at a first temperature for a first time period to induce material interactions at an accelerated rate, said runner fabricated according to said given fabrication process;

cooling said runner to a second temperature, and maintaining said second temperature for a time of sufficient duration such that relaxation occurs;

heating said runner at a third temperature for a time sufficient to nucleate a predetermined number of voids;

heating said runner at a fourth temperature, less than said third temperature and greater than room temperature, to propagate said voids such that a maximum void size is determined.

2. The method according to claim 1, further comprising the step of analyzing void size distribution as a function of said fourth temperature and time for heating at said fourth temperature to provide a measure of reliability for said conductive runner fabricated according to said given fabrication process.

3. The method according to claim 1, wherein the step of heating said runner at a third temperature includes observing void size distribution over time.

4. The method according to claim 1, wherein the step of heating said runner at a fourth temperature includes observing void size distribution over time.

5. The method according to claim 1, wherein the step of heating said runner at a first temperature includes observing said material interactions over time.

6. The method according to claim 5, wherein said material interactions include interdiffusion which are observed by elemental analysis techniques.

7. The method according to claim 1, wherein said third temperature is selected such that void nucleation results in at least about 80% of a maximum possible number of nucleated voids.

8. The method according to claim 1, wherein said conductive runner is surrounded by dielectric material.

9. The method according to claim 1, wherein said heating steps are applied to different conductive runner samples to provide an experimental test matrix of heating temperatures or times.

10. The method according to claim 1, wherein said heating and cooling steps are applied to different samples having conductive runners fabricated according to different processing parameters in order to optimize a fabrication process with respect to stress migration.

11. The method according to claim 10, wherein the different processing parameters include at least one of runner thickness, dielectric thickness, runner material, dielectric material, design rules, annealing cycles, runner deposition parameters, and dielectric deposition parameters.

12. The method according to claim 1, further comprising the step, subsequent to said step of heating at said third temperature, of cooling said conductive runner to a temperature less than said fourth temperature prior to the step of heating said runner at the fourth temperature.

13. A method for fabricating integrated circuits, comprising the steps of:

forming at least one conductive runner layer or at least one interlayer dielectric according to processing parameters predetermined based on executing a stress migration evaluation method on each of an array of conductive runner samples fabricated according to respective processing parameters, the stress migration evaluation method comprising the steps of;

heating the conductive runner sample at a first temperature for a first time period to induce material interactions at an accelerated rate;

cooling the conductive runner sample to a second temperature, and maintaining said second temperature for a time of sufficient duration such that relaxation occurs;

heating the conductive runner sample at a third temperature for a time sufficient to nucleate a predetermined number of voids;

heating the conductive runner sample at a fourth temperature, less than said third temperature and greater than room temperature, to propagate said voids such that a maximum void size is determined.

14. The method according to claim 13, wherein for each conductive runner sample fabricated according to respective processing parameters said heating steps are applied to different conductive runner sub-samples to provide an experimental test matrix of heating temperatures or times.

15. The method according to claim 13, wherein said step of forming at least one conductive runner layer or at least one interlayer dielectric includes the steps of depositing and patterning a first conductive material to provide a patterned conductive runner layer, and depositing an insulating layer over said patterned conductive runner layer.

16. The method according to claim 13, wherein the respective processing parameters include at least one of of runner thickness, dielectric thickness, runner material, dielectric material, design rules, annealing cycles, runner deposition parameters, and dielectric deposition parameters.

17. An integrated circuit comprising an interconnect conductive layer or an interlayer dielectric formed according to a process which is predetermined based on executing a stress migration evaluation method on each of an array of conductive runner samples fabricated according to respective processing parameters, the stress migration evaluation method comprising the steps of:

heating the conductive runner sample at a first temperature for a first time period to induce material interactions at an accelerated rate;

cooling the conductive runner sample to a second temperature, and maintaining said second temperature for a time of sufficient duration such that relaxation occurs;

heating the conductive runner sample at a third temperature for a time sufficient to nucleate a predetermined number of voids;

heating the conductive runner sample at a fourth temperature, less than said third temperature and greater than room temperature, to propagate said voids such that a maximum void size is determined.

18. The integrated circuit according to claim 17, wherein for each conductive runner sample fabricated according to respective processing parameters said heating steps are applied to different conductive runner sub-samples to provide an experimental test matrix of heating temperatures or times.

19. The integrated circuit according to claim 17, wherein said step of forming at least one conductive runner layer or at least one interlayer dielectric includes the steps of depositing and patterning a first conductive material to provide a patterned conductive runner layer, and depositing an insulating layer over said patterned conductive runner layer.

20. The integrated circuit according to claim 17, wherein the respective processing parameters include at least one of of runner thickness, dielectric thickness, runner material, dielectric material, design rules, annealing cycles, runner deposition parameters, and dielectric deposition parameters.