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Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure

DC
  • US 5,930,630 A
  • Filed: 07/23/1997
  • Issued: 07/27/1999
  • Est. Priority Date: 07/23/1997
  • Status: Expired due to Term
First Claim
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1. A method for fabricating a MOSFET transistor on a substrate comprising steps of:

  • a) forming an epi-layer of a first conductivity type as a drain region in said substrate and then growing an initial oxide layer over said epi-layer;

    (b) applying an active mask for etching said active layer to define an active area followed by depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates;

    (c) removing said polysilicon mask then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions;

    (d) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and a source diffusion process;

    (e) forming an overlying insulation layer covering said MOSFET device followed by applying a contact mask to open a plurality of contact openings there-through; and

    (f) performing a low energy body-dopant implant and high energy body dopant implant to form a self-aligned shallow high concentration body dopant region and a self-aligned deep high concentration body dopant region.

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