Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure

• US 5,930,630 A
• Filed: 07/23/1997
• Issued: 07/27/1999
• Est. Priority Date: 07/23/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Megamos Corporation
• Inventors: So, Kong Chong, Hshieh, Fwu-Iuan, Nim, Danny Chi
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/899,186
• Time in Patent Office: 734 Days
• Field of Search: 438/138, 438/156, 438/268, 438/273, 438/307, 438/529, 438/545
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention discloses method for fabricating a MOSFET on a substrate to improve device ruggedness. The method includes steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and growing an initial oxide layer over the epi-layer; (b) applying an active mask for etching the active layer to define an active area followed by depositing an overlaying polysilicon layer and applying a polysilicon mask for etching the polysilicon layer to define a plurality of polysilicon gates; (c) removing the mask and carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions; (d) applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the blocking mask and a source diffusion process; (e) forming an overlying insulation layer covering the MOSFET followed by applying a contact mask to open a plurality of contact openings; (f) performing a low energy body-dopant and high energy body dopant implant to form a shallow high-concentration body dopant and a deep high-concentration body dopant region followed by applying a high temperature process for densification of the insulation layer and activating diffusion of the deep and shallow body dopant regions wherein the deep high-concentration body-dopant regions are formed below the source regions and extends beyond the contact regions but are kept at lateral distance away from a channel region of the MOSFET in the body region whereby device ruggedness is improved without increasing threshold voltage.

Claims

1. A method for fabricating a MOSFET transistor on a substrate comprising steps of:

a) forming an epi-layer of a first conductivity type as a drain region in said substrate and then growing an initial oxide layer over said epi-layer;

(b) applying an active mask for etching said active layer to define an active area followed by depositing an overlaying polysilicon layer thereon and applying a polysilicon mask for etching said polysilicon layer to define a plurality of polysilicon gates;

(c) removing said polysilicon mask then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions;

(d) applying a source blocking mask for implanting a plurality of source regions in said body regions with ions of said first conductivity type followed by removing said source blocking mask and a source diffusion process;

(e) forming an overlying insulation layer covering said MOSFET device followed by applying a contact mask to open a plurality of contact openings there-through; and

(f) performing a low energy body-dopant implant and high energy body dopant implant to form a self-aligned shallow high concentration body dopant region and a self-aligned deep high concentration body dopant region.

2. The method for fabricating said MOSFET transistor of claim 1 wherein:

after forming said self-aligned shallow high concentration body-dopant region and said self-aligned deep high concentration body-dopant region, said step (f) further includes a step of applying a high temperature process for densffication of said insulation layer and for activating a diffusion of said deep and shallow high concentration body dopant regions.

3. The method for fabricating said MOSFET transistor of claim 1 further comprising:

(g) applying an etching process for removing a top portion of said substrate from said contact openings for providing a source contact area of lower contact resistance.

4. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (f) of performing a high energy body dopant implant to form a self-aligned deep body dopant region is a step of applying a channeling-effect implant by performing said high energy body dopant implant without an implant oxide layer.

5. The method for fabricating said MOSFET transistor of claim 1 wherein:

said step (f) of performing a high energy body dopant implant to form a self-aligned deep body dopant region is a step of applying a channeling-effect implant by performing said high energy body dopant implant at an implant angle of less than seven degrees from a perpendicular direction to a top surface of said substrate.

6. The method for fabricating said MOSFET transistor of claim 5 wherein:

said step (f) of performing a high energy body dopant implant to form a self-aligned deep body dopant region is a step of applying a channeling-effect implant by performing said high energy body dopant implant at an implant angle of zero degrees from a perpendicular direction to a top surface of said substrate.

7. The method for fabricating said MOSFET transistor of claim 4 wherein:

said step (f) is a step of applying said channeling-effect implant by skipping an implant oxide layer formation process and by performing said high energy body dopant implant at an implant angle of seven degrees from a perpendicular direction to a top surface of said substrate.