Method of making a low parasitic resistor on ultrathin silicon on insulator

• US 5,930,638 A
• Filed: 08/19/1997
• Issued: 07/27/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/914,474
• Time in Patent Office: 707 Days
• Field of Search: 438/149, 438/151, 438/152, 438/382, 438/383, 438/384, 438/238, 148/DIG. 136
• US Class Current: 438/382
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/136 Resistors

Abstract

A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer. Both non-silicide and silicide processes are disclosed. Also disclosed is a differential amplifier circuit that uses the disclosed diffused resistor embodiments.

Claims

1. A method for forming a diffused resistor comprising the steps of:

providing an insulating substrate;

forming a thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×

10¹¹ cm^-2 ;

providing any resistor implants in a resistive region of the thin semiconductor layer wherein the any resistor implants are for setting a resistance of the diffused resistor;

preventing any implants other than the any resistor implants from being provided in the resistive region;

forming in the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region.

2. The method of claim 1, further comprising the steps of:

forming an electrically isolated portion of the thin semiconductor layer wherein the electrically isolated portion of the thin semiconductor layer has the maximum fixed charge density of no more than about 5×

10¹¹ cm^-2 ;

after forming the electrically isolated portion of the thin semiconductor layer, forming the first and second contact regions and the resistive region in the electrically isolated portion.

3. The method of claim 1, wherein the thin semiconductor layer comprises a thin silicon layer.

4. The method of claim 1, wherein the thickness of the semiconductor layer is no more than about 1,500 angstroms.

5. The method of claim 1, wherein the thickness of the thin semiconductor layer is in a range of about 500-1500 angstroms.

6. The method of claim 1, wherein the thickness of the thin semiconductor layer is no more than about 1,100 angstroms.

7. The method of claim 1, wherein the insulating substrate comprises sapphire.

8. The method of claim 1, wherein the maximum fixed charge density is no more than about 3×

10¹¹ cm^-2.

9. The method of claim 1, wherein the maximum fixed charge density is in a range of about 2×

10¹¹ cm^-2 to about 5×

10¹¹ cm^-2.

10. The method of claim 1, wherein the step of providing any resistor implants in the resistive region comprises ion implanting a conductivity determining dopant into the resistive region.

11. The method of claim 10, wherein the step of providing any resistor implants in the resistive region dopes the resistive region N-type.

12. The method of claim 11, wherein the step of forming the first and second contact regions dopes the first and second contact regions N+type.

13. The method of claim 10, wherein the step of providing any resistor implants in the resistive region dopes the resistive region P-type.

14. The method of claim 13, wherein the step of forming the first and second contact regions dopes the first and second contact regions P+type.

15. The method of claim 1, wherein the step of providing any resistor implants in the resistive region comprises diffusion doping a conductivity determining dopant into the resistive region.

16. The method of claim 1, wherein no resistor implant is provided in the resistive region.

17. The method of claim 1, wherein the any resistive implants consist of a single dopant type.

18. The method of claim 1, wherein a resistance of the diffused resistor has an accuracy of ±

five percent.

19. The method of claim 1, wherein prior to providing the any resistor implants in the resistive region, the resistive region has a maximum fixed charge density such that the resistive region is capable of providing sheet resistances ranging from as low as about 30 Ω

/□

to as high as about 1,000,000,000 Ω

/□

.

20. The method of claim 1, wherein a resistance of the diffused resistor provides resistance matching to an accuracy of about ±

one percent.

21. The method of claim 1, wherein dimensions of the resistive region can be as small as a lithography limit of an initial masking step.

22. The method of claim 1, wherein the diffused resistor exhibits a temperature coefficient in the range of about -350 parts per million to about -75 parts per million.

23. The method of claim 1, wherein the diffused resistor exhibits a temperature coefficient in the range of about -350 parts per million to about -150 parts per million.

24. The method of claim 1, wherein the diffused resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -995 parts per million.

25. The method of claim 1, where in the diff used resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -950 parts per million.

26. The method of claim 1, wherein the diffused resistor exhibits a voltage coefficient in the range of about -1.2 parts per million to about -900 parts per million.

27. The method of claim 1, further comprising the steps of:

providing a silicide block over the resistive region wherein the silicide block is self-aligned with the first and second contact regions;

forming a first silicide region in the first contact region after providing the silicide block; and

forming a second silicide region in the second contact region after providing the silicide block.

28. A method for forming a diffused resistor and a MOSFET in a thin semiconductor layer, the method comprising the steps of:

providing an insulating substrate;

forming the thin semiconductor layer on the insulating substrate wherein the thin semiconductor layer has a maximum fixed charge density of no more than about 5×

10¹¹ cm^-2 ;

forming a first electrically isolated portion of the thin semiconductor layer and a second electrically isolated portion of the thin semiconductor layer wherein at least the first electrically isolated portion has the maximum fixed charge density of no more than about 5×

10¹¹ cm^-2 ;

providing any resistor implants in a resistive region of the first electrically isolated portion of the thin semiconductor layer wherein the resistor implants are for setting a resistance of the diffused resistor;

preventing any implants other than the any resistor implants from being provided in the resistive region;

forming in the first electrically isolated portion of the thin semiconductor layer a first contact region and a second contact region wherein the first contact region is electrically coupled to the resistive region by being contiguous with a first portion of the resistive region and wherein the second contact region is electrically coupled to the resistive region by being contiguous with a second portion of the resistive region;

forming a MOSFET in the second electrically isolated portion of the thin semiconductor layer.

29. The method of claim 28, wherein the step of forming the MOSFET in the second electrically isolated portion of the thin semiconductor layer comprises the steps of:

forming in the second electrically isolated portion a channel of the MOSFET;

forming a gate oxide adjacent to the channel;

forming a gate conductor adjacent to the gate oxide;

forming in the second electrically isolated portion a source of the MOSFET that is self-aligned by the gate oxide and the gate conductor; and

forming in the second electrically isolated portion a drain of the MOSFET that is self-aligned by the gate oxide and the gate conductor.

30. The method of claim 29, further comprising the step of:

providing the any resistor implant in the resistive region during a doping step that also dopes the channel of the MOSFET.

31. The method of claim 29, further comprising the step of:

doping the first and second contact regions during a doping step that also dopes the source and drain of the MOSFET.

32. The method of claim 29, further comprising the step of forming a first sidewall spacer and a second sidewall spacer each adjacent to the gate oxide and the gate conductor.

33. The method of claim 32, wherein the step of forming the source and drain of the MOSFET comprises the step of forming a lightly doped source self-aligned by the first sidewall spacer and a lightly doped drain self-aligned by the second sidewall spacer.

34. The method of claim 33, wherein the step of forming the source comprises the step of forming a silicide region in the source and the step of forming the drain comprises the step of forming a silicide region in the drain.

35. The method of claim 29, wherein step of forming the gate conductor comprises the step of forming a silicide region in the gate conductor.

36. The method of claim 32, wherein the step of forming the sidewall spacers also forms a silicide block over the resistive region.

37. The method of claim 36, further comprising the step of forming a silicide region in each of the source, the drain and the gate conductor after the step of forming the sidewall spacers and the silicide block.

38. The method of claim 28, wherein the thin semiconductor layer has a thickness of no more than about 1,500 angstroms.

39. The method of claim 28, wherein the step of providing any resistor implants in the resistive region of the first electrically isolated portion is performed after the step of forming the first electrically isolated portion of the thin semiconductor layer.