Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

• US 5,930,663 A
• Filed: 05/11/1998
• Issued: 07/27/1999
• Est. Priority Date: 09/22/1995
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Inventors: Baukus, James P., Clark, William M. Jr., Chow, Lap Wai
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Wille, Douglas A.
• Application Number:
  US09/076,012
• Time in Patent Office: 442 Days
• Field of Search: 257/390, 438/598, 438/514
• US Class Current: 438/598
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 27/02 including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.

Claims

1. A method of fabricating a camouflaged digital integrated circuit (IC), comprising:

implanting an array of transistors in a substrate, implanting common patterns of electrically conductive doped interconnections among said transistors, and

interrupting some of said interconnections in a manner that is not readily visibly perceptible to implement different logic functions for separate groups of transistors that have common transistor sizes and layouts.

2. The method of claim 1, wherein the interrupted interconnections are interrupted by implanting heavily doped channel stops of opposite conductivity into them.

3. The method of claim 2, wherein transistor and interconnection implants of the same conductivity are performed at the same time.

4. The method of claim 2, wherein transistor and channel stop implants of the same conductivity are performed at the same time.

5. The method of claim 2, wherein said channel stops are implanted with the smallest feature size of said transistors.

6. The method of claim 1, further comprising the steps of implanting electrically conductive doped taps from at least some of said transistors for receiving external connections, interrupting at least some of said taps in a manner that is not readily visibly perceptible, and providing external connections to said taps.

7. The method of claim 6, wherein said interrupted taps are interrupted by implanting electrically conductive doped channel stops into the taps of opposite conductivity to the tap doping.

8. The method of claim 7, wherein transistor and interrupted tap channel stops implants of the same conductivity are performed at the same time.

9. The method of claim 7, wherein said tap channel stops are implanted with the smallest feature size of said transistors.