Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO
First Claim
1. An interface circuit for use in one bit or multiple bit synchronization schemes is interposed between a first circuitry synchronous to a first clock and a second circuitry synchronous to a second clock for transferring data between the first circuitry and the second circuitry, said first and second clocks being asynchronous with respect to each other and said second clock being faster than said first clock, said interface circuit comprising:
- (a) a first buffer having a plurality of storage locations for transferring data from the first circuitry to the second circuitry, wherein the first circuitry writes to a storage location pointed to by a write pointer in the first buffer, and the second circuitry reads from a storage location pointed to by a read pointer in the first buffer;
(b) first synchronization means coupled to the first buffer for synchronizing writes and reads to the first buffer, said first synchronization means including a clock generator generating a synchronizing clock, said first synchronization means providing the synchronizing clock to a write port of the first buffer and to a write pointer generator generating the write pointer; and
(c) filled locations determining means coupled to said first synchronization means for dynamically determining how many storage locations are filled with data and for providing a plurality of flags, said flags indicating varying degrees of fullness of the first buffer to said second circuitry at every cycle of the second clock.
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Abstract
An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At-- least-- x-- words-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided. A write Bus Request Enable Generator provides a write bus request enable signal to the first circuitry, and an At-- least-- y-- words-- empty Flag Generator provides a plurality of flags, which indicate degrees of emptiness of the second buffer to the second circuitry.
51 Citations
31 Claims
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1. An interface circuit for use in one bit or multiple bit synchronization schemes is interposed between a first circuitry synchronous to a first clock and a second circuitry synchronous to a second clock for transferring data between the first circuitry and the second circuitry, said first and second clocks being asynchronous with respect to each other and said second clock being faster than said first clock, said interface circuit comprising:
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(a) a first buffer having a plurality of storage locations for transferring data from the first circuitry to the second circuitry, wherein the first circuitry writes to a storage location pointed to by a write pointer in the first buffer, and the second circuitry reads from a storage location pointed to by a read pointer in the first buffer; (b) first synchronization means coupled to the first buffer for synchronizing writes and reads to the first buffer, said first synchronization means including a clock generator generating a synchronizing clock, said first synchronization means providing the synchronizing clock to a write port of the first buffer and to a write pointer generator generating the write pointer; and (c) filled locations determining means coupled to said first synchronization means for dynamically determining how many storage locations are filled with data and for providing a plurality of flags, said flags indicating varying degrees of fullness of the first buffer to said second circuitry at every cycle of the second clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer system comprising:
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a host processor synchronous to a first clock; a memory coupled to the host processor; a system bus coupled to the host processor; a network card synchronous to a second clock and coupled to the system bus for allowing network communication, said first and second clocks being asynchronous with respect to each other and said second clock being faster than said first clock; and an interface circuit coupled to the system bus and said network card for transferring data between the system bus and the network card, said interface circuit including; (a) a first buffer having a plurality of storage locations for transferring data from the first circuitry to the second circuitry, wherein the first circuitry writes to a storage location pointed to by a write pointer in the first buffer, and the second circuitry reads from a storage location pointed to by a read pointer in the first buffer; (b) first synchronization means coupled to the first buffer for synchronizing writes and reads to the first buffer, said first synchronization means including a clock generator generating a synchronizing clock, said first synchronization means providing the synchronizing clock to a write port of the first buffer and to a write pointer generator generating the write pointer; and (c) filled locations determining means coupled to said first synchronization means for dynamically determining how many storage locations are filled with data and for providing a plurality of flags, said flags indicating varying degrees of fullness of the first buffer to said second circuitry at every cycle of the second clock. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. An interface circuit for use in one bit or multiple bit synchronization scheme is interposed between a first circuitry synchronous to a first clock and a second circuitry synchronous to a second clock for transferring data between the first circuitry and the second circuitry, said first and second clocks being asynchronous with respect to each other and said second clock being faster than said first clock, said interface circuit comprising:
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(a) a first buffer having a plurality of storage locations for transferring data from the first circuitry to the second circuitry, wherein the first circuitry writes to a storage location pointed to by a write pointer in the first buffer, and the second circuitry reads from a storage location pointed to by a read pointer in the first buffer; (b) first synchronization circuit coupled to the first buffer for synchronizing writes and reads to the first buffer, said first synchronization circuit including a clock generator generating a synchronizing clock, said first synchronization circuit providing the synchronizing clock to a write port of the first buffer and to a write pointer generator generating the write pointer; and (c) filled locations determining logic coupled to said first synchronization circuit for dynamically determining how many storage locations are filled with data and for providing a plurality of flags, said flags indicating varying degrees of fullness of the first buffer to said second circuitry at every cycle of the second clock.
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31. A computer system comprising:
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a host processor synchronous to a first clock; a memory coupled to the host processor; a system bus coupled to the host processor; a network card synchronous to a second clock and coupled to the system bus for allowing network communication, said first and second clocks being asynchronous with respect to each other and said second clock being faster than said first clock; and an interface circuit coupled to the system bus and said network card for transferring data between the system bus and the network card, said interface circuit including; (a) a first buffer having a plurality of storage locations for transferring data from the first circuitry to the second circuitry, wherein the first circuitry writes to a storage location pointed to by a write pointer in the first buffer, and the second circuitry reads from a storage location pointed to by a read pointer in the first buffer; (b) first synchronization circuit coupled to the first buffer for synchronizing writes and reads to the first buffer, said first synchronization circuit including a clock generator generating a synchronizing clock, said first synchronization circuit providing the synchronizing clock to a write port of the first buffer and to a write pointer generator generating the write pointer; and (c) filled locations determining logic coupled to said first synchronization circuit for dynamically determining how many storage locations are filled with data and for providing a plurality of flags, said flags indicating varying degrees of fullness of the first buffer to said second circuitry at every cycle of the second clock.
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Specification