Trench EPROM

• US 5,932,908 A
• Filed: 12/11/1996
• Issued: 08/03/1999
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Noble, Wendell Phillips
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/760,090
• Time in Patent Office: 965 Days
• Field of Search: 257/318, 257/315, 257/323, 365/149, 365/185.01, 365/185.18
• US Class Current: 257/315
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.

Claims

1. A semiconductor chip comprising a nonvolatile memory cell having a vertical floating gate adjacent a vertical channel of a vertical FET and a buried diffusion surrounding said floating gate, said buried diffusion serving as a control electrode, said floating gate capacitively coupled predominantly to said buried diffusion.

2. A semiconductor chip as recited in claim 1, wherein said non-volatile memory cell comprises a planar FET in series with a vertical floating gate FET.

3. A semiconductor chip as recited in claim 2, wherein said vertical floating gate FET shares a diffusion with said planar FET.

4. A semiconductor chip as recited in claim 1, further comprising a DRAM memory cell, wherein said non-volatile memory cell and said DRAM memory cell cover substantially equal surface areas on the chip.

5. A semiconductor chip as recited in claim 4, wherein said non-volatile memory cell is formed in a process substantially included in the process of fabricating said DRAM memory cell.