Input protective circuit having a diffusion resistance layer

• US 5,932,917 A
• Filed: 04/10/1997
• Issued: 08/03/1999
• Est. Priority Date: 04/19/1996
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Nippon Steel Corporation
• Inventors: Miura, Hirotomo
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/834,840
• Time in Patent Office: 845 Days
• Field of Search: 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363, 257/546, 257/547, 257/489, 438/527
• US Class Current: 257/358
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

An input protective circuit includes a resistance element for connecting the input terminal and internal circuit of a semiconductor integrated circuit, and a field effect transistor for discharging a surge input to the ground potential. Adjacent diffusion layer regions consisting of a diffusion resistance layer corresponding to the resistance element and an impurity diffusion layer corresponding to the drain or source of the field effect transistor and connected adjacent to each other are formed by double diffusion using ion implantation.

Claims

1. An input protective circuit having a resistance element with one end connected to an input terminal of a semiconductor integrated circuit and the other end connected to an internal circuit, and a field effect transistor consisting of a source and drain for forming a channel between the other end of said resistance element and a reference voltage conductor and a gate covering said channel, comprising:

a first diffusion layer region including a first impurity diffusion layer corresponding to said drain of said field effect transistor and a first diffusion resistance layer corresponding to said resistance element adjacent said first impurity diffusion layer;

a second diffusion layer region including a second impurity diffusion layer corresponding to said source of said field effect transistor and a second diffusion resistance layer adjacent said second impurity diffusion layer, and

a conductor for connecting an end portion of said second diffusion resistance layer to said gate.

2. A circuit according to claim 1, wherein said first diffusion resistance layer and said first impurity diffusion layer are formed to have the same conductivity type and different conductivities.

3. A circuit according to claim 1, wherein said semiconductor integrated circuit is formed on a p-type semiconductor substrate, said first impurity diffusion layer is of an n⁺ type, and said first diffusion resistance layer is of an n^- type.

4. A circuit according to claim 1, wherein said input protective circuit is formed in a single element active region.

5. A circuit according to claim 1, wherein said gate of said field effect transistor is connected to said reference voltage conductor.

6. A circuit according to claim 1, wherein said second diffusion resistance layer and said second impurity diffusion layer are formed to have the same conductivity type and different conductivities.

7. A circuit according to claim 1, wherein said semiconductor integrated circuit is formed on a p-type semiconductor substrate, said second impurity diffusion layer is of an n⁺ type, and said second diffusion resistance layer is of an n^- type.