Input protective circuit having a diffusion resistance layer
First Claim
1. An input protective circuit having a resistance element with one end connected to an input terminal of a semiconductor integrated circuit and the other end connected to an internal circuit, and a field effect transistor consisting of a source and drain for forming a channel between the other end of said resistance element and a reference voltage conductor and a gate covering said channel, comprising:
- a first diffusion layer region including a first impurity diffusion layer corresponding to said drain of said field effect transistor and a first diffusion resistance layer corresponding to said resistance element adjacent said first impurity diffusion layer;
a second diffusion layer region including a second impurity diffusion layer corresponding to said source of said field effect transistor and a second diffusion resistance layer adjacent said second impurity diffusion layer, anda conductor for connecting an end portion of said second diffusion resistance layer to said gate.
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Accused Products
Abstract
An input protective circuit includes a resistance element for connecting the input terminal and internal circuit of a semiconductor integrated circuit, and a field effect transistor for discharging a surge input to the ground potential. Adjacent diffusion layer regions consisting of a diffusion resistance layer corresponding to the resistance element and an impurity diffusion layer corresponding to the drain or source of the field effect transistor and connected adjacent to each other are formed by double diffusion using ion implantation.
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Citations
7 Claims
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1. An input protective circuit having a resistance element with one end connected to an input terminal of a semiconductor integrated circuit and the other end connected to an internal circuit, and a field effect transistor consisting of a source and drain for forming a channel between the other end of said resistance element and a reference voltage conductor and a gate covering said channel, comprising:
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a first diffusion layer region including a first impurity diffusion layer corresponding to said drain of said field effect transistor and a first diffusion resistance layer corresponding to said resistance element adjacent said first impurity diffusion layer; a second diffusion layer region including a second impurity diffusion layer corresponding to said source of said field effect transistor and a second diffusion resistance layer adjacent said second impurity diffusion layer, and a conductor for connecting an end portion of said second diffusion resistance layer to said gate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification