FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines

• US 5,933,023 A
• Filed: 09/03/1996
• Issued: 08/03/1999
• Est. Priority Date: 09/03/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Young, Steven P.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/708,247
• Time in Patent Office: 1,064 Days
• Field of Search: 326/37, 326/39-41, 326/46-47
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and control lines in the RAM blocks. Thus, the logic blocks of the FPGA can use these routing lines to access portions of RAM. In one embodiment, dedicated address and data lines access the RAM blocks of the present invention and are connectable to routing lines in the interconnect structure. These lines allow RAM blocks and arrays of RAM blocks to be configured long, wide, or in between, and allow logic blocks to conveniently access RAM blocks in a remote part of the chip. Access to the RAM blocks is efficient in any RAM configuration. Bidirectional buffers or pass devices segment the address and data lines at each RAM block so that a selectable number of RAM blocks can operate together as a RAM. In another embodiment, dedicated data lines are programmably connectable in a staggered arrangement so that RAM blocks can be connected over a long distance without conflict between the RAM blocks.

Claims

1. An FPGA with RAM comprising:

a plurality of logic blocks arranged in rows and columns;

a plurality of RAM blocks dedicated to the RAM function and arranged in columns, said RAM blocks having address ports and data ports;

an interconnect structure comprising conductive lines arranged in rows;

a set of vertical lines for carrying only address signals, each line in the set of vertical lines programmably driving said address ports of a column of more than one of said RAM blocks;

means for connecting said logic blocks to said interconnect structure;

means for connecting said vertical lines to said interconnect structure; and

means for connecting said address ports to said vertical lines.

2. An FPGA with RAM as in claim 1 further comprising:

means for segmenting said vertical lines.

3. An FPGA with RAM as in claim 2 wherein some of said means for segmenting are bidirectional buffers.

4. An FPGA with RAM as in claim 2 wherein some of said means for segmenting are pass transistors.

5. An FPGA with RAM as in claim 3 wherein said bidirectional buffers segment a line into line segments, each segment being adjacent to a RAM block.

6. An FPGA with RAM as in claim 1 wherein some of said RAM blocks comprise dual port RAMs having two address ports and at least two data ports, all such address ports being accessible by said vertical lines.

7. An FPGA with RAM as in claim 1 wherein each of said RAM blocks can be configured to a plurality of length-to-width ratios.

8. An FPGA with RAM as in claim 1 wherein each of said RAM blocks spans four logic blocks.

9. An FPGA with RAM as in claim 2, further comprising:

a group of vertical data lines for carrying only data signals, each group programmably driving said data ports of a column of more than one of said RAM blocks;

means for connecting said data lines to said interconnect structure;

means for connecting said data ports to said data lines; and

means for segmenting said data lines;

wherein a first one of said RAM blocks is connectable to different ones of said data lines from a second one of said RAM blocks vertically adjacent to said first RAM block.

10. An FPGA with RAM as in claim 9 wherein a first one of said group of data lines driving said first RAM block can be connected without utilizing said interconnect structure to a different one of said group of data lines driving said second RAM block such that a signal driving a given data port in said first RAM block does not conflict with a signal driving the same given data port in said second RAM block.

11. An FPGA with RAM blocks comprising:

a plurality of logic blocks arranged in rows and columns;

a plurality of general interconnect lines;

a plurality of RAM blocks each comprising;

a plurality of RAMs dedicated to the RAM function, each being addressed by a dedicated address bus and accessed by at least one dedicated data bus, and being enabled by at least one enable line; and

means for connecting each line in each of said address bus and said data bus to at least one of said general interconnect lines; and

means for programmably connecting each enable line, each line in each of said address bus and said at least one data bus in one of said RAM blocks to a corresponding line in another of said RAM blocks, whereby a larger RAM is formed having a programmable configuration;

said data bus in one of said RAM blocks being connected to a data bus in another of said RAM blocks through a tristatable bidirectional connector.

12. An FPGA as in claim 11 in which said means for programmably connecting each enable line, each line in each of said address bus and said at least one data bus in one of said RAM blocks to a corresponding line in another of said RAM blocks comprises a bidirectional buffer for making each programmable connection.

13. An FPGA as in claim 11 in which said means for programmably connecting each enable line, each line in each of said address bus and said at least one data bus in one of said RAM blocks to a corresponding line in another of said RAM blocks comprises a pass gate for making each programmable connection.

14. An FPGA as in claim 11 in which said means for programmably connecting each enable line, each line in each of said address bus and said at least one data bus in one of said RAM blocks to a corresponding line in another of said RAM blocks comprises at least one bidirectional buffer for making a corresponding at least one programmable connection, and at least one pass transistor for making a corresponding at least one programmable connection.

15. An FPGA as in claim 14 in which said at least one bidirectional buffer comprises bidirectional buffers for connecting all lines which provide input signals to one of said RAMs and said at least one pass transistor comprises pass transistors for connecting all lines which provide output from one of said RAMs.

16. An FPGA as in claim 11 in which said at least one enable line is a plurality of enable lines providing input signals to a decoder 132!.

17. An FPGA with RAM blocks comprising:

a plurality of logic blocks arranged in rows and columns;

a plurality of general interconnect lines;

a plurality of RAM blocks each comprising;

a plurality of RAMs dedicated to the RAM function, each being addressed by an address bus and accessed by at least one data bus, and being enabled by at least one enable line; and

means for connecting each line in each of said address bus and said data bus to at least one of said general interconnect lines; and

means for programmably connecting each enable line, each line in each of said address bus and said at least one data bus in one of said RAM blocks to a corresponding line in another of said RAM blocks, whereby a larger RAM is formed having a programmable configuration,

wherein;

said data bus in one of said RAM blocks is connected to a data bus in another of said RAM blocks through a tristatable bidirectional connector;

said at least one enable line is a plurality of enable lines providing input signals to a decoder; and

said decoder comprises a plurality of multiplexers each controlled by one of said enable lines, said multiplexers each receiving a plurality of multiplexer input signals having a selectable value.

18. An FPGA as in claim 17 in which said multiplexer input signals are each stored in a memory cell.

19. An FPGA with RAM comprising:

a plurality of logic blocks arranged in rows and columns;

a plurality of RAM blocks dedicated to the RAM function and arranged in columns, said RAM blocks having address ports and data ports;

an interconnect structure comprising conductive lines arranged in rows;

a set of vertical lines for carrying only data signals, each line in the set of vertical lines programmably driving said data ports of a column of more than one of said RAM blocks;

means for connecting said logic blocks to said interconnect structure;

means for connecting said vertical lines to said interconnect structure; and

means for connecting said data ports to said vertical lines.

20. An FPGA with RAM as in claim 19 further comprising:

means for segmenting said vertical lines.

21. An FPGA with RAM as in claim 20 wherein some of said means for segmenting are bidirectional buffers.

22. An FPGA with RAM as in claim 20 wherein some of said means for segmenting are pass transistors.

23. An FPGA with RAM as in claim 21 wherein said bidirectional buffers segment a line into line segments, each segment being adjacent to a RAM block.

24. An FPGA with RAM as in claim 19 wherein some of said RAM blocks comprise dual port RAMs having two address ports and at least two data ports, all such data ports being accessible by said vertical lines.

25. An FPGA with RAM as in claim 19 wherein each of said RAM blocks can be configured to a plurality of length-to-width ratios.

26. An FPGA with RAM as in claim 19 wherein each of said RAM blocks spans four logic blocks.