Semiconductor integrated circuit device comprising a bias circuit, a driver circuit, and a receiver circuit

• US 5,933,029 A
• Filed: 04/28/1997
• Issued: 08/03/1999
• Est. Priority Date: 04/30/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakurai, Takayasu, Kuroda, Tadahiro
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US08/848,126
• Time in Patent Office: 827 Days
• Field of Search: 326/83, 326/86, 326/26, 326/27, 326/30, 326/31, 326/32, 326/33, 326/34, 327/541, 327/543, 327/143, 327/198
• US Class Current: 326/86
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/30111 matching
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first/supply voltage and the second supply voltage.

Claims

1. A semiconductor integrated circuit device, comprising:

a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage;

a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating from an output voltage of said bias circuit to the first supply voltage and visa versa, and for driving a transfer path by the converted signal;

a voltage divider circuit for dividing an output voltage of said bias circuit; and

a receiver circuit for detecting the signal for driving the transfer path by use of an output of said voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.

2. The semiconductor integrated circuit device of claim 1, wherein said bias circuit comprises:

a series circuit composed of a plurality of series-connected same-conductivity type MOS transistors each having a gate and a drain connected to each other; and

another MOS transistor having a conductivity type the same as that of the series-connected MOS transistors; and

wherein a source side of the transistor of the series-connected circuit is connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit is connected to a current source and a gate of the other MOS transistor;

a drain of the other MOS transistor is connected to the second supply voltage; and

a bias voltage is outputted from a source of the other MOS transistor.

3. A semiconductor integrated circuit device, comprising:

a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage;

a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating from an output voltage of said bias circuit to the first supply voltage and visa versa on the basis of an enable signal, and for driving a transfer path by the converted signal or for setting an output thereof to a high impedance;

a voltage divider circuit for dividing an output voltage of said bias circuit; and

a receiver circuit for detecting the signal for driving the transfer path by use of an output of said voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.

4. The semiconductor integrated circuit device of claim 3, which further comprises a bus terminator circuit for, when the output of said driver circuit is set to the high impedance, maintaining the voltage of the transfer path at a value of the output of said driver circuit just before the output of said driver circuit is set to the high impedance.

5. The semiconductor integrated circuit device of claim 3, wherein said bias circuit comprises:

a series circuit composed of a plurality of series-connected same-conductivity type MOS transistors each having a gate and a drain connected to each other; and

another MOS transistor having a conductivity type the same as that of the series-connected MOS transistors; and

wherein a source side of the transistor of the series-connected circuit is connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit is connected to a current source and a gate of the other MOS transistor;

a drain of the other MOS transistor is connected to the second supply voltage; and

a bias voltage is outputted from a source of the other MOS transistor.

6. A semiconductor integrated circuit device, comprising:

a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage;

a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into two differential signals each vibrating from an output voltage of said bias circuit to the first supply voltage and visa versa, and for driving two transfer paths by the two differential signals, respectively; and

a receiver circuit for detecting the differential signals for driving the transfer paths, and for converting the detected differential signals into a signal vibrating between the first supply voltage and the second supply voltage.

7. The semiconductor integrated circuit device of claim 6, wherein said bias circuit comprises:

a series circuit composed of a plurality of series-connected same-conductivity type MOS transistors each having a gate and a drain connected to each other; and

another MOS transistor having a conductivity type the same as that of the series-connected MOS transistors; and

wherein a source side of the transistor of the series-connected circuit is connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit is connected to a current source and a gate of the other MOS transistor;

a drain of the other MOS transistor is connected to the second supply voltage; and

a bias voltage is outputted from a source of the other MOS transistor.

8. A semiconductor integrated circuit device, comprising:

a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage;

a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into two differential signals each vibrating from an output voltage of said bias circuit to the first supply voltage and visa versa on the basis of an enable signal, and for driving two transfer paths by the two differential signals or for setting two outputs thereof to a high impedance, respectively; and

a receiver circuit for detecting the differential signals for driving the transfer paths, and for converting the detected differential signals into a signal vibrating between the first supply voltage and the second supply voltage.

9. The semiconductor integrated circuit device of claim 8, which further comprises a bus terminator circuit for, when the output of said driver circuit is set to the high impedance, maintaining the voltage of the transfer path at a value of the output of said driver circuit just before the output of said driver circuit is set to the high impedance.

10. The semiconductor integrated circuit device of claim 8, wherein said bias circuit comprises:

a series circuit composed of a plurality of series-connected same-conductivity type MOS transistors each having a gate and a drain connected to each other; and

another MOS transistor having a conductivity type the same as that of the series-connected MOS transistors; and

wherein a source side of the transistor of the series-connected circuit is connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit is connected to a current source and a gate of the other MOS transistor;

a drain of the other MOS transistor is connected to the second supply voltage; and

a bias voltage is outputted from a source of the other MOS transistor.

11. A semiconductor integrated circuit device, comprising:

a first semiconductor chip including;

a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage;

a first driver circuit for receiving a first inversion input signal and a first non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of said bias circuit and the first supply voltage on the basis of a first enable signal, and for outputting the converted signal or for setting an output thereof to a high impedance;

a first voltage divider circuit for dividing an output voltage of said bias circuit; and

a first receiver circuit; and

a second semiconductor chip including;

a second voltage divider circuit having an input end connected to an input end of said first voltage divider circuit via a wire, for dividing an output voltage of said bias circuit;

a second driver circuit having an output end connected to an output end of said first driver circuit via a transfer wire, for receiving a second inversion input signal and a second non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of said bias circuit and the first supply voltage on the basis of a second enable signal, and for outputting the converted signal or for setting an output thereof to a high impedance; and

a second receiver circuit; and

wherein;

said first receiver circuit is activated, when the output of said first driver circuit is at the high impedance, to detect a signal transferred from said second driver circuit via the transfer wire and further to convert the detected signal into a signal vibrating between the first supply voltage and the second supply voltage; and

said second receiver circuit is activated, when the output of said second driver circuit is at the high impedance, to detect a signal transferred from said first driver circuit via the transfer wire and further to convert the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.

12. The semiconductor integrated circuit device of claim 11, wherein said bias circuit comprises:

a series circuit composed of a plurality of series-connected same-conductivity type MOS transistors each having a gate and a drain connected to each other; and

another MOS transistor having a conductivity type the same as that of the series-connected MOS transistors; and

wherein a source side of the transistor of the series-connected circuit is connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit is connected to a current source and a gate of the other MOS transistor;

a drain of the other MOS transistor is connected to the second supply voltage; and

a bias voltage is outputted from a source of the other MOS transistor.

13. The semiconductor integrated circuit device of claim 11, wherein the wire for connecting said first voltage dividing circuit and said second voltage dividing circuit is any one of a bonding wire, a substrate wire and a bus.

14. The semiconductor integrated circuit device of claim 11, wherein the transfer wire for connecting said first driver circuit and said second driver circuit is any one of a bonding wire, a substrate wire and a bus.

18. The semiconductor integrated circuit device of claim 11, wherein the wire for connecting said first voltage dividing circuit and said second voltage dividing circuit is a bus, the transfer wire for connecting said first drive circuit and said second drive circuit is a bus, and said first and second semiconductor chips are arranged to be laminated one upon another.

15. A semiconductor integrated circuit device, comprising:

a first semiconductor chip including;

a first bias circuit for generating a predetermined fixed voltage between a first supply voltage and a second supply voltage;

a first driver circuit for receiving a first inversion input signal and a first non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into two differential signals each vibrating from an output voltage of said first bias circuit to the first supply voltage and visa versa on the basis of a first enable signal, and for outputting the converted differential signals or setting two outputs thereof to a high impedance, respectively; and

a first receiver circuit; and

a second semiconductor chip including;

a second bias circuit for generating another predetermined voltage fixed between a third supply voltage and a fourth supply voltage;

a second driver circuit for receiving a second inversion input signal and a second non-inversion input signal each vibrating between the third and fourth supply voltages, for converting the received input signals into two differential signals each vibrating between an output voltage of said second bias circuit and the third supply voltage on the basis of a second enable signal, and for outputting the converted differential signals or setting two outputs thereof to a high impedance, respectively; and

a second receiver circuit; and

wherein;

two output ends of each of said first and second driver circuits are connected to each other by a transfer wire, respectively;

said first receiver circuit is activated, when the output of said first driver circuit is at the high impedance, to detect the two differential signals transferred from said second driver circuit via the transfer wires and further to convert the detected difference signals into a signal vibrating between the first supply voltage and the second supply voltage; and

said second receiver circuit is activated, when the output of said second driver circuit is at the high impedance, to detect the two differential signals transferred from said first driver circuit via the transfer wire and further to convert the detected differential signals into a signal vibrating between the third supply voltage and the fourth supply voltage.

16. The semiconductor integrated circuit device of claim 15, wherein said first bias circuit comprises:

a series circuit composed of a plurality of series-connected first-conductivity type MOS transistors each having a gate and a drain connected to each other;

another first-conductivity type MOS transistor; and

a source side of the transistor of the series-connected circuit being connected to the first supply voltage;

a drain side of the transistor of the series-connected circuit being connected to a current source and a gate of the other first-conductivity type MOS transistor; and

a drain of the other first conductivity-type MOS transistor being connected to the second supply voltage; and

a bias voltage being outputted from a source of the first-conductivity type MOS transistor, and

wherein said second bias circuit comprises;

a series circuit composed of a plurality of series-connected second-conductivity type MOS transistors each having a gate and a drain connected to each other;

another second-conductivity type MOS transistor; and

a source side of the transistor of the series-connected circuit being connected to the third supply voltage;

a drain side of the transistor of the series-connected circuit being connected to a current source and a gate of the other second-conductivity type MOS transistor; and

a drain of the other second conductivity-type MOS transistor being connected to the fourth supply voltage; and

a bias voltage being outputted from a source of the second-conductivity type MOS transistor.

17. The semiconductor integrated circuit device of claim 15, wherein the transfer wire for connecting said first driver circuit and said second driver circuit is any one of a bonding wire, a substrate wire and a bus.

19. The semiconductor integrated circuit device of claim 15, wherein the transfer wire for connecting said first drive circuit and said second drive circuit is a bus, and said first and second semiconductor chips are arranged to be laminated one upon another.

20. The semiconductor integrated circuit device of claim 16, wherein the transfer wire for connecting said first drive circuit and said second drive circuit is a bus, and said first and second semiconductor chips are arranged to be laminated one upon another.