Programmable delay line

• US 5,933,039 A
• Filed: 03/25/1997
• Issued: 08/03/1999
• Est. Priority Date: 12/07/1992
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Mounger, Robert W., Hui, Titkwan
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/823,708
• Time in Patent Office: 861 Days
• Field of Search: 327/261, 327/262, 327/263, 327/269, 327/270, 327/276, 327/271, 327/272, 327/278, 327/231, 327/237, 327/258
• US Class Current: 327/262
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00084 by trimming or adjusting the delay
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width

Abstract

Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Claims

1. An integrated circuit comprising:

an input terminal for receiving a string of digital pulses;

an output terminal for transmitting the so received digital pulses;

a means to temperature compensate a voltage source;

a delay cell by use of a variable resistance which comprises a program selection of resistor strings coupled to said input terminal and said output terminal for passing a string of digital pulses inputted from said input terminal to said output terminal;

an adjustable load; and

a programmable memory coupled to said variable resistance and said adjustable load, for storing a plurality of data bits wherein said data bits are used for controlling the amount of delay time of said delay cell.