Use of a link bit to fetch entries of a graphic address remapping table

• US 5,933,158 A
• Filed: 09/09/1997
• Issued: 08/03/1999
• Est. Priority Date: 09/09/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Elliott, Robert C., Santos, Gregory N.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Luu, Sy D.
• Application Number:
  US08/926,426
• Time in Patent Office: 693 Days
• Field of Search: 345/503, 345/520-521, 345/514, 345/522, 345/526, 345/515, 345/516, 345/507, 345/509, 711/206-207, 711/202, 395/306-309, 395/310
• US Class Current: 345/568
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in the computer system physical memory, and feature flags that may be used to customize the associated page of graphics data. One of the feature flags is used as a link bit for each GART table entry such that when the core logic chipset reads selected ones of the GART table entries stored in the system memory, it stores a first one of the selected ones in its cache memory and determines if the link bit thereof is set. If the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in the cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in the cache memory until one of the link bits thereof is determined not to be set.

Claims

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

a system processor executing software instructions and generating graphics data;

a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;

the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;

an accelerated graphics port (AGP) processor, said AGP processor generating video display data from the graphics data for display on a video display;

a core logic chipset;

said core logic chipset having a first interface logic for connecting said system processor to said system memory;

said core logic chipset having a second interface logic for connecting said system processor and said system memory to said AGP processor;

said core logic chipset having a cache memory; and

a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding one of the plurality of pages of graphics data and a link bit for determining if selected ones of the plurality of GART table entries are related;

wherein

said core logic chipset reads the selected ones of the plurality of GART table entries and stores a first one of the selected ones in said cache memory and determines if the link bit thereof is set, if the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in said cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in said cache memory until one of the link bits thereof is determined not to be set; and

,

said core logic chipset uses the selected ones of the plurality of GART table entries stored in said cache memory to point to associated pages of a first portion of the graphics data stored in said system memory, the associated pages of the first portion of the graphics data being read by said core logic chipset and reordered into a contiguous AGP device address space for use by said AGP processor to generate the video display data.

2. The computer system of claim 1, further comprising said core logic having a third interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus.

3. The computer system of claim 2, further comprising said core logic having a fourth interface logic for connecting said AGP processor to said PCI bus.

4. The computer system of claim 1, wherein said system processor is a plurality of system processors.

5. The computer system of claim 1, further comprising a local frame buffer memory connected to said AGP processor, said local frame buffer storing a second portion of the graphics data from said system memory.

6. The computer system of claim 5, wherein said local frame buffer memory stores the second portion of the graphics data in the contiguous AGP device address space and said AGP processor accesses the first portion of the graphics data in the contiguous AGP device address space by using the GART table entries stored in said cache memory and accesses the second portion of the graphics data from said local frame buffer memory.

7. The computer system of claim 6, wherein said graphics processor reads the first and second portions of the graphics data in the contiguous AGP device address space.

8. The computer system of claim 1, wherein the plurality of pages of graphics data are stored in said system memory in a non-contiguous and random order.

9. The computer system of claim 1, wherein said plurality of GART table entries are stored in said system memory.

10. The computer system of claim 1, wherein the plurality of GART table entries are stored in a plurality of pages of GART table entries in said system memory.

11. The computer system of claim 10, wherein said plurality of pages of GART table entries are stored in said system memory in a non-contiguous and random order.

12. The computer system of claim 11, further comprising a GART directory having a plurality of entries, each of the plurality of GART directory entries comprising an address pointer to a corresponding one of the plurality of pages of GART table entries, wherein said core logic chipset uses the plurality of GART directory entries for locating the plurality of pages of GART table entries in said system memory.

13. The computer system of claim 1, wherein the number of the plurality of bytes of storage in each of the plurality of pages of graphics data is 4096 bytes.

14. The computer system of claim 1, wherein said core logic chipset is at least one integrated circuit.

15. The computer system of claim 14, wherein said at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

16. The computer system of claim 14, wherein said at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

17. The computer system of claim 1, further comprising a video display.

18. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard, and a mouse.

19. The computer system of claim 1, further comprising a serial port, a parallel port, a keyboard and a real time clock.

20. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

21. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, said system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a random access memory bus;

a core logic chipset having a cache memory and connected to the host bus and the random access memory bus;

said core logic chipset configured as a first interface bridge between the host bus and the random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect (PCI) bus, and a third interface bridge between the random access memory bus and the first PCI bus;

said core logic chipset configured as a fourth interface bridge between the host bus and an accelerated graphics port (AGP) bus; and

said core logic chipset configured as a fifth interface bridge between the random access memory bus and the AGP bus;

wherein,

said core logic chipset uses a graphics address remapping table (GART table) having a plurality of entries stored in said random access memory, each of the plurality of GART table entries comprising an address pointer to an corresponding one of a plurality of pages of graphics data stored in said random access memory and a link bit for determining if selected ones of the plurality of GART table entries are related; and

said core logic chipset reads the selected ones of the plurality of GART table entries stored in said random access memory, wherein said core logic chipset stores a first one of the selected ones in said cache memory and determines if the link bit thereof is set, if the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in said cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in said cache memory until one of the link bits thereof is determined not to be set.

22. The computer system of claim 21, wherein the central processing unit is a plurality of central processing units.

23. The computer system of claim 21, wherein the plurality of pages of graphics data are stored in said random access memory in a non-contiguous and random order.

24. The computer system of claim 23, wherein each one of the plurality of GART table entries comprises a plurality of binary bits and each one of the plurality of pages of graphics data is associated with the each one of the plurality of GART table entries such that a first number of most significant bits of the plurality of binary bits comprise a base address of the corresponding each one of the plurality of pages of graphics data.

25. The computer system of claim 24, wherein a bit of a second number of least significant bits of the plurality of binary bits comprises the link bit for the corresponding each one of the plurality of pages of graphics data.

26. The computer system of claim 21, wherein the plurality of GART table entries are stored in at least one page of said random access memory.

27. The computer system of claim 21, wherein each of the plurality of pages of graphics data is 4096 bytes.

28. The computer system of claim 21, wherein said central processing unit executes software instructions and generates the graphics data.

29. The computer system of claim 21, further comprising a graphics processor for generating video display data from the graphics data.

30. The computer system of claim 29, further comprising a local frame buffer memory coupled to said graphics processor, wherein said graphics processor combines video data stored in said local frame buffer memory with the corresponding ones of the plurality of pages of graphics data read from said random access memory based upon the selected ones of the plurality of GART table entries stored in said cache memory to generate video display data.

31. The computer system of claim 21, wherein said core logic chipset prefetches from said random access memory the selected ones of the plurality of GART table entries to said cache memory.

32. A method, in a computer system, of dynamically fetching from the computer system memory the correct number of selected ones of a plurality of graphics address remapping table (GART table) entries to a cache memory, said method comprising the steps of:

(a) storing a plurality of graphics data pages in any order in a system memory of a computer system;

(b) storing a graphics address remapping table (GART table) having a plurality of entries in the system memory, each of the plurality of GART table entries comprising an address pointer to an associated one of the plurality of graphics data pages stored in the system memory and a link bit used to associate together certain ones of the plurality of GART table entries;

(c) reading a selected one of the plurality of GART table entries stored in the system memory;

(d) determining if the link bit is set in the selected one read from the system memory;

(e) storing the selected one read from the system memory into a cache memory; and

(f) repeating steps (c) through (e) by reading a next selected one of the plurality of GART table entries if the link bit is set in the previously read selected one.

33. The method of claim 32, further comprising the step of reading the plurality of graphics data pages in an order determined by the selected ones of the plurality of GART table entries.

34. The method of claim 32, wherein a system memory address is determined for each byte of graphics data stored in the plurality of graphics data pages by the base address stored in the associated one of the plurality of GART table entries and an offset address added to the base address.

35. The method of claim 32, further comprising the step of setting the link bit of at least one of the plurality of GART table entries by an application programming interface.

36. The method of claim 35, further comprising the step of reading the link bit of the at least one of the plurality of GART table entries by the application programming interface.

37. The method of claim 32, further comprising the step of allocating memory locations in the system during computer system initialization for storing the plurality of GART table entries.

38. A method, in a computer system, of dynamically fetching from the computer system memory the correct number of selected ones of a plurality of graphics address remapping table (GART table) entries to a cache memory for the purpose of remapping random, non-contiguous graphics data pages stored in the system memory into a contiguous graphics device address space, said method comprising the steps of:

(a) storing a plurality of graphics data pages in any order in a system memory of a computer system;

(b) storing a graphics address remapping table (GART table) having a plurality of entries in the system memory, each of the plurality of GART table entries comprising an address pointer to an associated one of the plurality of graphics data pages stored in the system memory and a link bit used to associate together certain ones of the plurality of GART table entries;

(c) reading a selected one of the plurality of GART table entries stored in the system memory;

(d) determining if the link bit is set in the selected one read from the system memory;

(e) storing the selected one read from the system memory into a cache memory;

(f) repeating steps (c) through (e) by reading a next selected one of the plurality of GART table entries if the link bit is set in the previously read selected one; and

(g) reading the graphics data pages stored in system memory in the order of the selected ones of the plurality of GART table entries stored in the cache memory, wherein the graphics data pages read are translated to a contiguous graphics device address space.

39. The method of claim 38, further comprising the step of generating video display data with a graphics processor by the graphics processor reading the graphics data pages in the contiguous graphics device address space.

40. The method of claim 39, further comprising the steps of:

requesting new graphics data pages in the contiguous graphics device address space by the graphics processor;

determining if the cache memory contains the selected ones of the plurality of GART table entries associated with the new graphics data pages;

if the cache memory does not contain the selected ones then fetch the selected ones according to steps (c) through (f); and

if the cache memory contains the selected ones then perform step (g).

41. A core logic chipset adapted for connection to a computer processor and memory, an accelerated graphics port (AGP) bus and a peripheral component interconnect (PCI) bus, comprising:

an accelerated graphics port (AGP) request queue;

an AGP reply queue;

an AGP data and control logic;

an AGP cache memory;

an AGP arbiter;

a host to peripheral component interconnect (PCI) bridge;

a PCI to PCI bridge;

a memory interface and control logic adapted for connection to a computer system random access memory; and

a host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto;

wherein,

said AGP request and reply queues are connected to said memory interface and control logic;

said AGP data and control logic is connected to said memory and interface control logic;

said AGP data and control logic is connected to a host bus interface;

said host to PCI bus bridge is connected to said host bus interface and adapted for connection to a computer system PCI bus;

said PCI to PCI bridge connected to said AGP data and control logic, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to PCI bus bridge and said AGP data and control logic;

said AGP data and control logic and said AGP arbiter adapted for connection to an AGP bus having an AGP device;

wherein,

said AGP data and control logic is adapted to use a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of entries comprising an address pointer to a one of a plurality of pages of graphics data in the computer system random access memory and a link bit for determining if selected ones of the plurality of GART table entries are associated together; and

said AGP data and control logic adapted to read the selected ones of the plurality of GART table entries stored in the computer system random access memory, wherein said AGP data and control logic stores a first one of the selected ones in said AGP cache memory and determines if the link bit thereof is set, if the link bit of the first one of the selected ones is set then a next one of the selected ones is stored in said AGP cache memory and if the link bit thereof is set then a subsequent one of the selected ones is stored in said AGP cache memory until one of the link bits thereof is determined not to be set.