Microprocessor having timer circuit generating complementary non-overlapped PWM signals
First Claim
1. A circuit in a single chip microcomputer, comprising:
- a first register storing a first value;
a second register storing a second value larger than the first value;
a third register storing a third value larger than the second value, wherein the difference between the second value and the third value corresponds to the first value;
a first counter receiving clock signals, wherein the first counter generates a count value by counting up and down between the first value and the third value by counting the clock signals;
a second counter receiving the clock signals, wherein the second counter generates a count value by counting up and down between a fourth value smaller than the first value and the second value by counting the clock signals, wherein the difference between the first value and the fourth value corresponds to the first value, wherein the difference between the count value of the first counter and the count value of the second counter corresponds to the first value, wherein the second counter counts up when the first counter counts up, and wherein the second counter counts down when the first counter counts down;
a third counter receiving the clock signals, wherein the third counter generates a count value by counting up and down between the first value and the fourth value and between the third value and the second value by counting the clock signals, wherein the third counter begins to count down from the third value when the count value of the first counter matches the second value, wherein the third counter begins to count up from the second value when the count value of the second counter matches the second value, wherein the third counter begins to count up from the fourth value when the count value of the second counter matches the first value, and wherein the third counter begins to count down from the first value when the count value of the first counter matches the first value;
a fourth register storing a fifth value between the fourth value and the third value;
an up-down control circuit coupled to the first, second and third counters and controlling up and down counting of the first, second and third counters;
a compare circuit, wherein the compare circuit compares the fifth value with the respective count values of the first and second counters when the fifth value is between the first value and the second value, wherein the compare circuit compares the fifth value with the respective count values of the first counter counting up and the third counter counting up or with the respective count values of the first counter counting down and the third counter counting down when the fifth value is larger than the second value, and wherein the compare circuit compares the fifth value with the respective count values of the second counter counting down and the third counter counting down or with the respective count values of the second counter counting up and the third counter counting up when the fifth value is smaller than the second value, wherein complementary non-overlapped PWM signals are generated.
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Accused Products
Abstract
Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.
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Citations
19 Claims
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1. A circuit in a single chip microcomputer, comprising:
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a first register storing a first value; a second register storing a second value larger than the first value; a third register storing a third value larger than the second value, wherein the difference between the second value and the third value corresponds to the first value; a first counter receiving clock signals, wherein the first counter generates a count value by counting up and down between the first value and the third value by counting the clock signals; a second counter receiving the clock signals, wherein the second counter generates a count value by counting up and down between a fourth value smaller than the first value and the second value by counting the clock signals, wherein the difference between the first value and the fourth value corresponds to the first value, wherein the difference between the count value of the first counter and the count value of the second counter corresponds to the first value, wherein the second counter counts up when the first counter counts up, and wherein the second counter counts down when the first counter counts down; a third counter receiving the clock signals, wherein the third counter generates a count value by counting up and down between the first value and the fourth value and between the third value and the second value by counting the clock signals, wherein the third counter begins to count down from the third value when the count value of the first counter matches the second value, wherein the third counter begins to count up from the second value when the count value of the second counter matches the second value, wherein the third counter begins to count up from the fourth value when the count value of the second counter matches the first value, and wherein the third counter begins to count down from the first value when the count value of the first counter matches the first value; a fourth register storing a fifth value between the fourth value and the third value; an up-down control circuit coupled to the first, second and third counters and controlling up and down counting of the first, second and third counters; a compare circuit, wherein the compare circuit compares the fifth value with the respective count values of the first and second counters when the fifth value is between the first value and the second value, wherein the compare circuit compares the fifth value with the respective count values of the first counter counting up and the third counter counting up or with the respective count values of the first counter counting down and the third counter counting down when the fifth value is larger than the second value, and wherein the compare circuit compares the fifth value with the respective count values of the second counter counting down and the third counter counting down or with the respective count values of the second counter counting up and the third counter counting up when the fifth value is smaller than the second value, wherein complementary non-overlapped PWM signals are generated. - View Dependent Claims (2, 3, 4, 5)
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6. A timer circuit, included in a single-chip microcomputer, for generating complementary non-overlapped pulse width modulation signals, comprising:
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a first register storing a first value; a second register storing a second value larger than the first value; a third register storing a third value larger than the second value, wherein the difference between the second value and the third value corresponds to the first value; a first counter receiving clock signals, wherein the first counter generates a count value by counting up and down between the first value and the third value by counting the clock signals; a second counter receiving the clock signals, wherein the second counter generates a count value by counting up and down between a fourth value smaller than the first value and the second value by counting the clock signals, wherein the difference between the first value and the fourth value corresponds to the first value, wherein the difference between the count value of the first counter and the count value of the second counter corresponds to the first value, wherein the second counter counts up when the first counter counts up, and wherein the second counter counts down when the first counter counts down; a third counter receiving the clock signals, wherein the third counter generates a count value by counting up and down between the first value and the fourth value and between the third value and the second value by counting the clock signals, wherein the third counter begins to count down from the third value when the count value of the first counter matches the second value, wherein the third counter begins to count up from the second value when the count value of the second counter matches the second value, wherein the third counter begins to count up from the fourth value when the count value of the second counter matches the first value, and wherein the third counter begins to count down from the first value when the count value of the first counter matches the first value; a fourth register storing a fifth value between the fourth value and the third value, wherein the fifth value is selectively changed by a central processing unit; an up-down control circuit coupled to the first, second and third counters and controlling up and down counting of the first, second and third counters; a compare circuit, wherein the compare circuit compares the fifth value with the respective count value of the first and second counters when the fifth value is between the first value and the second value, wherein the compare circuit compares the fifth value with the respective count value of the first counter counting up and the third counter counting up or with the respective count value of the first counter counting down and the third counter counting down when the fifth value is greater than the second value, and wherein the compare circuit compares the fifth value with the respective count value of the second counter counting down and the third counter counting down or with the respective count value of the second counter counting up and the third counter counting up when the fifth value is less than the second value, wherein complementary non-overlapped PWM signals are generated. - View Dependent Claims (7, 8, 9, 10)
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11. In a semiconductor integrated circuit, a method for producing complementary non-overlapping PWM signals, comprising the steps of:
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counting between a first value and a third value with a first counter; counting between a fourth value and a second value with a second counter; wherein the first value is greater than the fourth value, the second value is greater than the first value, and the third value is greater than the second value; counting between the second value and the third value and between the first value and the fourth value with a third counter, wherein the third counter counts down from the third value when the count value of the first counter matches the second value, wherein the third counter counts up from the second value when the count value of the second counter matches the second value, wherein the third counter counts up from the fourth value when the count value of the second counter matches the first value, and wherein the third counter counts down from the first value when the count value of the first counter matches the first value; storing a fifth value; generating the complementary non-overlapped PWM signals, wherein the step of generating the complementary non-overlapped PWM signals comprises the steps of comparing the fifth value with the respective count values of the first and second counters when the fifth value is between the first value and the second value, comparing the fifth value with the respective count values of the first counter counting up and the third counter counting up or with the respective count values of the first counter counting down and the third counter counting down when the fifth value is larger than the second value, and comparing the fifth value with the respective count values of the second counter counting down and the third counter counting down or with the respective count values of the second counter counting up and the third counter counting up when the fifth value is smaller than the second value. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification