Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models

• US 5,933,356 A
• Filed: 11/05/1996
• Issued: 08/03/1999
• Est. Priority Date: 04/06/1990
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dangelo, Carlos, Rostoker, Michael D., Bair, Owen S.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/740,967
• Time in Patent Office: 1,001 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 703/15
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.

Claims

1. An ECAD system for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising:

a compiler for compiling the VHDL description of the circuit or device;

means for locating problems within said compiled description and measuring the effectiveness of solving said problems;

means for passing information including said compiled description to a physical design level;

a physical design tool for receiving said information and creating a physical design therefrom; and

means for back annotating information from the physical design tool to the compiler.

2. The system of claim 1, wherein said information received by said physical design tool comprises timing information relating to the physical design.

3. The system of claim 1, further comprising a verification tool to verify design choices made by said physical design tool.

4. The system of claim 1, further comprising a simulation tool to simulate design description functionality.

5. A constraint analyzer for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising:

means for receiving library data and a gate-level netlist;

means for receiving information including a VHDL representation of the device or circuit; and

a gate level power analysis tool for exploring device or circuit power design tradeoffs based on library data, the gate level netlist, and the VHDL representation of the circuit or device.

6. A compiling tool for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising:

means for receiving predetermined device or circuit parameters; and

a synthesizing element for synthesizing circuits by simultaneously optimizing predetermined constraints based on said predetermined parameters and creating a constraint optimized gate-level netlist of said circuits.

7. The compiling tool of claim 6, wherein said predetermined constraints comprise at least one from the group of timing, area, and power.

8. A method for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising the steps of:

compiling the VHDL description of the circuit or device;

locating problems within said compiled description and measuring the effectiveness of solving said problems;

passing information including said compiled description to a physical design level;

receiving said information and creating a physic design therefrom; and

back annotating information from the physical design tool to the compiler.

9. The method of claim 8, wherein said information received by said receiving and creating step comprises timing information relating to the physical design.

10. The method of claim 8, further comprising verifying design choices made by said receiving and creating step.

11. The method of claim 10, further comprising simulating design description functionality.

12. A method of creating and validating an electronic design from a behavioral description thereof, comprising the steps of:

providing a behavioral description of the electronic design;

simulating and changing the behavioral description of the design;

partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and

creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.

13. A system for creating and validating an electronic design from a behavioral description thereof, comprising:

a simulation tool for simulating and changing the behavioral description of the design;

a partitioning tool for partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and

a physical design tool creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.