Continuous synchronization adjustment in a telecommunications system

• US 5,933,468 A
• Filed: 03/06/1997
• Issued: 08/03/1999
• Est. Priority Date: 03/06/1997
• Status: Expired due to Term

• Current Assignee: Unwired Planet LLC (JP Morgan Chase & Co)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Kingdon, Christopher Hugh
• Primary Examiner(s): LE, AMANDA T
• Application Number:
  US08/813,029
• Time in Patent Office: 880 Days
• Field of Search: 375/354, 375/362, 375/364, 375/365, 375/368, 370/503, 370/505, 370/506, 370/509, 370/510, 370/512, 370/514, 370/520
• US Class Current: 375/362
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines

Abstract

A continuous synchronization adjustment algorithm is described, which continuously synchronizes frames used in digital synchronous transmissions. By letting the receiver continuously adjust the assumed frame position, rather than adjusting only once per frame as conventionally done, a significant increase in bit error rate can be achieved. When an incorrect single sync bit is detected in a frame, thereafter during the rest of the frame, the single sync bit positions that would result from an advance or delay of the frame position (e.g., due to a bit slip in the frame) are checked. The frame position is then adjusted immediately, without waiting for the beginning of the next frame. Consequently, there is a significant decrease in the number of data bits that are interpreted incorrectly or disregarded. As such, the bit error rate resulting from the present continuous algorithm is significantly improved over that resulting from prior synchronization algorithms.

Claims

1. A method for use in synchronizing a sequence of transmitted and received symbols in a telecommunications system, comprising the steps of:

detecting an incorrect value of a first received symbol from said sequence of received symbols;

detecting at least one value of a second received symbol and a third received symbol from said sequence of received symbols; and

synchronizing said sequence of transmitted and received symbols by performing at least one step of advancing said sequence of received symbols if said second received symbol has an incorrect value, and delaying said sequence of received symbols if said third received symbol has an incorrect value.

2. The method of claim 1, wherein said sequence of received symbols comprises a frame.

3. The method of claim 1, wherein said sequence of received symbols comprises a TRAU frame.

4. The method of claim 3, wherein said telecommunications system comprises the GSM.

5. The method of claim 1, wherein said first received symbol comprises a single sync bit in a TRAU frame.

6. The method of claim 1, wherein said incorrect value comprises a logic value of "0".

7. The method of claim 1, wherein said second received symbol comprises a single sync bit position that is delayed in time with respect to said first received symbol.

8. The method of claim 1, wherein said third received symbol comprises a single sync bit position that is earlier in time than said first received symbol.

9. The method of claim 1, wherein said incorrect value of said first received symbol comprises a bit slip.

10. The method of claim 1, wherein said synchronizing step comprises inserting a plurality of dummy symbols in said sequence of symbols.

11. The method of claim 1, wherein said synchronizing step comprises skipping a plurality of symbols.

12. An apparatus for use in synchronizing a sequence of bits in a received frame in a mobile communications system, comprising:

a digital processor operable to;

detect an incorrect value of a first received single sync bit position from said sequence of bits in said received frame;

detect at least one value of a second received single sync bit position and a third received single sync bit position from said sequence of bits in said received frame; and

synchronize said sequence of received bits in said received frame by at least one of advancing said sequence of bits in said received frame if said second received single sync bit position has an incorrect value, and delaying said sequence of bits in said received frame if said third received single sync bit position has an incorrect value.

13. The apparatus of claim 12, wherein said digital processor comprises a DSP.

14. The apparatus of claim 12, wherein said digital processor comprises an Application Specific Integrated Circuit (ASIC).