Isolation of PCI and EISA masters by masking control and interrupt lines
First Claim
1. A computer system, comprising:
- a host processor connected to a host bus;
a bus bridge connecting said host bus to a system expansion bus;
a system management module connected to said system expansion bus, said system management module including;
a system management processor connected to a system management local bus;
a system management central control unit connected to said system management local bus and to the expansion system bus;
wherein said system management central control unit includes an arbiter and monitor logic which operates as a bus arbiter for the expansion bus, and interrupt routing logic for selectively routing interrupt requests to the host processor originating from components on the expansion bus.
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Accused Products
Abstract
A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.
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Citations
45 Claims
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1. A computer system, comprising:
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a host processor connected to a host bus; a bus bridge connecting said host bus to a system expansion bus; a system management module connected to said system expansion bus, said system management module including; a system management processor connected to a system management local bus; a system management central control unit connected to said system management local bus and to the expansion system bus; wherein said system management central control unit includes an arbiter and monitor logic which operates as a bus arbiter for the expansion bus, and interrupt routing logic for selectively routing interrupt requests to the host processor originating from components on the expansion bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A computer system, comprising:
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a host processor connected to a host bus; a bus bridge connecting said host bus to a PCI bus; a system management module connected to said PCI bus, said system management module including a system management central control unit connected to said PCI bus; wherein said system management central control unit includes an arbiter and monitor logic which operates as a PCI bus arbitration unit, and said arbiter and monitor logic receives requests for mastership of the PCI bus from PCI master devices connected to the PCI bus, and said arbiter and monitor logic monitors the PCI bus to determine if any components connected to the PCI bus have failed. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A computer system, comprising:
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a host processor connected to a host bus; a bus bridge connecting said host bus to a PCI bus; a system management module connected to said PCI bus, said system management module including a system management central control unit connected to said PCI bus; wherein said system management central control unit includes monitor logic to monitor the PCI bus to determine if any components connected to the PCI bus have failed, and interrupt routing logic for selectively routing interrupt request to the host processor originating from components on the PCI bus, said interrupt routing logic capable of isolating failed devices on the PCI bus. - View Dependent Claims (40, 41)
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42. A computer system, comprising:
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a host processor connected to a host bus; a bus bridge connecting said host bus to a PCI bus; a second bus bridge connected to said PCI bus and to a system expansion bus; a system management module connected to said PCI bus, said system management module including a system management central control unit connected to said PCI bus; said system management central control unit including interrupt routing logic for selectively routing interrupt requests to the host processor; a system management remote unit connected to said system expansion bus, said system management remote unit connecting to said interrupt routing logic by a serial bus; and said second bus bridge connects to said interrupt logic by an interrupt bus, and said second bus bridge relays interrupt requests from devices connected to the system expansion bus. - View Dependent Claims (43, 44, 45)
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Specification