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Isolation of PCI and EISA masters by masking control and interrupt lines

  • US 5,933,614 A
  • Filed: 12/31/1996
  • Issued: 08/03/1999
  • Est. Priority Date: 12/31/1996
  • Status: Expired due to Term
First Claim
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1. A computer system, comprising:

  • a host processor connected to a host bus;

    a bus bridge connecting said host bus to a system expansion bus;

    a system management module connected to said system expansion bus, said system management module including;

    a system management processor connected to a system management local bus;

    a system management central control unit connected to said system management local bus and to the expansion system bus;

    wherein said system management central control unit includes an arbiter and monitor logic which operates as a bus arbiter for the expansion bus, and interrupt routing logic for selectively routing interrupt requests to the host processor originating from components on the expansion bus.

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