Compiling system and method for reconfigurable computing

• US 5,933,642 A
• Filed: 04/09/1997
• Issued: 08/03/1999
• Est. Priority Date: 04/17/1995
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited, Ricoh Corporation (Ricoh Company Limited)
• Original Assignee: Ricoh Company Limited, Ricoh Corporation (Ricoh Company Limited)
• Inventors: Baxter, Michael A., Greenbaum, Jack E.
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Chavis, John Q.
• Application Number:
  US08/827,619
• Time in Patent Office: 846 Days
• Field of Search: 395/709, 395/880.07, 395/800.39
• US Class Current: 717/140
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 8/47 Retargetable compilers
• CPC Class Codes: G06F 8/54 Link editing before load time
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading

Abstract

A compiling system and method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable among a plurality of hardware architectures, each hardware architecture executing instructions from a corresponding instruction set. Source files are compiled for execution using various instruction set architectures as specified by reconfiguration directives. Object files optionally encapsulate bitstreams specifying hardware architectures corresponding to instruction set architectures with executable code for execution on the architectures.

Claims

1. A compiling method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable during execution of the sequence of program instructions among a plurality of hardware architectures, each hardware architecture executing instructions from a corresponding instruction set, the compiling method comprising:

a) accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;

b) identifying a first instruction set for the first subset of instruction statements by retrieving a first reconfiguration directive from the source code, the reconfiguration directive specifying the first instruction set;

c) identifying a second instruction set for the second subset of instruction statements by retrieving a second reconfiguration directive from the source code, the reconfiguration directive specifying the second instruction set; and

d) compiling the first subset of instruction statements for execution using the first instruction set and compiling the second subset of instruction statements for execution using the second instruction set;

wherein each of the reconfiguration directive specifies a change in hardware organization to occur during program execution.

2. The method of claim 1, wherein each reconfiguration directive is provided using a meta-syntax.

3. The method of claim 1, wherein each reconfiguration directive comprises one of an immediate reconfiguration directive, a function-level reconfiguration directive, and a default reconfiguration directive.

4. The method of claim 1, further comprising:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the instruction set corresponding to the subset of instruction statements.

5. The method of claim 1, further comprising:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reference designating a bitstream representing the instruction set corresponding to the subset of instruction statements.

6. The method of claim 1, further comprising:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a reference encoded according to an extended executable and linking format, the reference designating a bitstream representing the instruction set corresponding to the subset of instruction statements.

7. The method of claim 1, further comprising:

e) generating an executable file including the results of d) and further including, for each subset of instruction statements, a bitstream representing the instruction set corresponding to the subset of instruction statements.

8. The method of claim 1, further comprising:

e) generating a first object file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the instruction set corresponding to the subset of instruction statements;

f) repeating a) through e) for at least a second source file to generate at least a second object file; and

g) linking the object files generated in e) and f) to generate an executable file.

9. The method of claim 8, further comprising:

h) performing memory alignment on the generated executable file according to alignment requirements.

10. The method of claim 9, wherein the generated executable file is associated with a bitstream representing an instruction set, and wherein h) comprises:

h.1) padding the bitstream to perform memory alignment.

11. The method of claim 8, wherein:

a) comprises accepting as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements, wherein at least one of the instruction statements contains an external reference; and

e) comprises generating a first object file including the results of d) and further including, for each subset of instruction statements, a reconfiguration code identifying the instruction set corresponding to the subset of instruction statements, wherein at least one of the instruction statements contains an external reference;

and further comprising;

f.1) prior to g), resolving the external references of each object file.

12. The method of claim 1, wherein the first subset of instruction statements comprises a first defined function and the second subset of instruction statements comprises a second defined function.

13. The method of claim 1, wherein the first subset of instruction statements comprises a first arbitrary block of statements and the second subset of instruction statements comprises a second arbitrary block of statements.

14. The method of claim 13, wherein the source file includes at least one function call and function return, and wherein steps b) and c) each comprise selectively performing inter-procedural analysis to identify an incontext instruction set architecture at each function call and function return.

15. The method of claim 1, further comprising:

e) optimizing the first compiled subset of instruction statements for the first instruction set; and

f) optimizing the second compiled subset of instruction statements for the second instruction set.

16. A compiling method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable during execution of the sequence of program instructions among a plurality of hardware architectures, each hardware architecture executing instructions from a corresponding instruction set, the compiling method comprising:

a) selecting a source code instruction statement from a source file containing a plurality of source code instruction statements;

b) responsive to the statement comprising a function call, performing the steps of;

b.1) determining a first instruction set currently in context;

b.2) determining a second instruction set for the function call;

b.3) responsive to the first instruction set being different than the second instruction set, performing the steps of;

b.3.1) emitting code statements for reconfiguration to the second instruction set;

b.3.2) emitting a compiled code statement for the function call; and

b.3.3) emitting code statements for reconfiguration to the first instruction set; and

b.4) responsive to the first instruction set architecture being identical to the second instruction set, emitting a compiled code statement for the function call;

c) responsive to the statement not comprising a function call, emitting a compiled code statement for the statement; and

d) repeating a) through c) for each source code instruction statement in the source file.

17. The method of claim 16, wherein b.3.1) comprises:

b.3.1.1) emitting a code statement for saving live registers; and

b.3.1.2) emitting a reconfiguration code statement;

and b.3.3) comprises;

b.3.3.1) emitting a reconfiguration code statement; and

b.3.3.2) emitting a code statement for restoring the saved live registers.

18. The method of claim 17, wherein the code statements comprise register transfer level statements.

19. The method of claim 18, further comprising:

e) performing register allocation;

f) for each register transfer level statement;

f.1) determining whether a translation rule exists for the register transfer level statement; and

f.2) responsive to a determination that a translation rule exists, generating assembly code for the register transfer level statement according to the translation rule.

20. The method of claim 18, further comprising:

e) annotating each register transfer level statement to indicate an instruction set architecture;

f) optimizing the register transfer level statements; and

g) generating machine-depending assembly code from the optimized register transfer level statements.

21. A method of reconfiguring a dynamically reconfigurable processing unit during execution of a program comprising a sequence of program instructions, the method comprising:

a) identifying a reconfiguration directive from the source code, the reconfiguration directive specifying a new instruction set;

b) storing a state of the program execution;

c) loading the new instruction set;

d) retrieving at least a portion of the stored state of the program execution; and

e) resuming execution using the new instruction set;

wherein the reconfiguration directive specifies a change in hardware organization to occur during program execution.

22. The method of claim 21 wherein b) comprises:

b.1) storing state variables on a stack referenced by a stack pointer; and

b.2) storing the stack pointer in a memory location; and

d) comprises;

d.1) retrieving the stack pointer from the memory location; and

d.2) retrieving the state variables from the stack.

23. A compiling system for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively changeable during execution of the sequence of program instructions among a plurality of hardware architectures, each hardware architecture executing instructions from a corresponding instruction set, the compiling system comprising:

an input device for inputting at least one source file containing a plurality of source code instruction statements, including at least a first subset of instruction statements, a second subset of instruction statements, and, for each subset of instruction statements a reconfiguration directive specifying one of the hardware architectures, each of the reconfiguration directives specifying a change in hardware organization to occur during program execution; and

a compiler, coupled to receive each source file from the input device, for compiling each input source file to produce an object file by identifying the instruction set corresponding to the hardware architecture specified by each reconfiguration directive, compiling at least a portion of the input source file for execution using each identified instruction set, and generating a reconfiguration code corresponding to each reconfiguration directive.

24. The compiling system of claim 23, further comprising:

a linker, coupled to receive each object file, for combining the object files to generate an executable file containing, for each reconfiguration directive, a reference to a bitstream describing the hardware architecture specified by the reconfiguration directive and a sequence of program instructions for the described hardware architecture.

25. The compiling system of claim 23, further comprising:

a linker, coupled to receive each object file, for combining the object files to generate an executable file containing, for each reconfiguration directive, a bitstream describing the hardware architecture specified by the reconfiguration directive and a sequence of program instructions for the described hardware architecture.

26. A computer program product comprising a computer-usable medium having computer-readable code embodied therein for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit, comprising:

computer-readable program code devices configured to accept as input a source file containing a plurality of source code instruction statements including at least a first subset of instruction statements and a second subset of instruction statements;

computer-readable program code devices configured to identify a first instruction set for the first subset of instruction statements by retrieving a first reconfiguration directive from the source code, the reconfiguration directive specifying the first instruction set;

computer-readable program code devices configured to identify a second instruction set for the second subset of instruction statements by retrieving a second reconfiguration directive from the source code, the reconfiguration directive specifying the second instruction set; and

computer-readable program code devices configured to compile the first subset of instruction statements for execution using the first instruction set and compiling the second subset of instruction statements for execution using the second instruction set,

wherein each of the reconfiguration directives specifies a change in hardware organization to occur during program execution.

27. The computer program product of claim 26, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a reconfiguration code identifying the instruction set corresponding to the subset of instruction statements.

28. The computer program product of claim 26, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a reference designating a bitstream representing the instruction set corresponding to the subset of instruction statements.

29. The computer program product of claim 26, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a reference encoded according to an extended executable and linking format, the reference designating a bitstream representing the instruction set corresponding to the subset of instruction statements.

30. The computer program product of claim 26, further comprising:

computer-readable program code devices configured to generate an executable file including the compiled statements and further including, for each subset of instruction statements, a bitstream representing the instruction set corresponding to the subset of instruction statements.

31. The computer program product of claim 26, further comprising:

computer-readable program code devices configured to generate a first object file including the compiled statements and further including, for each subset of instruction statements, a reconfiguration code identifying the instruction set corresponding to the subset of instruction statements;

computer-readable program code devices configured to generate at least a second object file; and

computer-readable program code devices configured to link the generated object files generated to generate an executable file.

32. The computer program product of claim 31, further comprising:

computer-readable program code devices configured to perform memory alignment on the generated executable file according to alignment requirements.