Alignment and ordering of vector elements for single instruction multiple data processing

• US 5,933,650 A
• Filed: 10/09/1997
• Issued: 08/03/1999
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Huffman, William A., Moreton, Henry P., Killian, Earl A., Van Hook, Timothy J., Hsu, Peter
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US08/947,649
• Time in Patent Office: 663 Days
• Field of Search: 395/800.22, 395/800.23, 395/800.2, 395/800.16, 395/800.02, 395/800.04, 395/376, 395/565, 395/566, 395/580, 395/380, 345/501, 345/502, 345/503, 345/506, 345/522, 345/191, 345/193, 345/197, 345/517
• US Class Current: 712/2
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled
• CPC Class Codes: G06F 7/76 Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

Claims

1. In a computer system including a processor having a plurality of registers, a method for generating an aligned vector of first width from two second width vectors for single instruction multiple data (SIMD) processing, comprising the steps of:

loading a first vector from a memory unit into a first register from a memory unit into a first register, wherein the first vector contains a first byte of an aligned vector to be generated;

loading a second vector from the memory unit into a second register;

determining a starting byte in the first register wherein the starting byte specifies the first byte of an aligned vector and wherein the starting byte is specified as a constant in an alignment instruction;

extracting a first width vector from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register; and

replicating the extracted first width vector into a third register such that the third register contains a plurality of elements aligned for SIMD processing.

2. The method as recited in claim 1 further comprising the step of storing the aligned vector in the third register to the memory unit.

3. The method as recited in claim 1, wherein the first width and second width are each 64 bits.

4. The method as recited in claim 3, wherein the third register is comprised of 8 8-bit elements.

5. The method as recited in claim 3, wherein the third register is comprised of 4 16-bit elements.

6. The method as recited in claim 1, wherein the starting byte is specified as a variable in a register in an alignment instruction.

7. The method as recited in claim 1, wherein the first vector and the second vector are in contiguous location in the memory unit.

8. The method as recited in claim 1, wherein the processor operates in a big-endian byte ordering mode.

9. The method as recited in claim 1, wherein the processor operates in a little-endian byte ordering mode.

10. In a computer system including a processor having a plurality of registers, a method for generating an ordered set of elements in an N-bit vector from two sets of elements in two N-bit vectors for single instruction multiple data (SIMD) vector processing, said method comprising the steps of:

loading a first vector from a memory unit into a first register;

loading a second vector from the memory unit into a second register;

wherein the first vector and the second vector are each comprised of 4 16-bit elements indexed from 0 to 3;

selecting a subset of elements from the first register and the second register wherein the subset is comprised of the elements 2 and 3 from the first register and the elements 2 and 3 from the second register; and

replicating the elements from the subset into the elements in the third register in a particular order suitable for subsequent SIMD vector processing, wherein the particular order of the elements in the third register comprises;

the element 0 replicated from the element 2 of the second register;

the element 1 replicated from the element 2 of the first register;

the element 2 replicated from the element 3 of the second register; and

the element 3 replicated from the element 3 of the first register.

11. The method as recited in claim 10, wherein the first vector and the second vector are each comprised of 8 8-bit elements indexed from 0 to 7.

12. The method as recited in claim 11, wherein the subset is comprised of four elements from the first register and four elements from the second register.

13. The method as recited in claim 11, wherein the subset is comprised of the elements 1, 3, 5, and 7 from the first register and the elements 1, 3, 5, and 7 from the second register.

14. The method as recited in claim 13, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 1 of the second register;

the element 1 replicated from the element 3 of the second register;

the element 2 replicated from the element 5 of the second register;

the element 3 replicated from the element 7 of the second register;

the element 4 replicated from the element 1 of the first register;

the element 5 replicated from the element 3 of the first register;

the element 6 replicated from the element 5 of the first register; and

the element 7 replicated from the element 7 of the first register.

15. The method as recited in claim 11, wherein the subset is comprised of the elements 0, 2, 4, and 6 from the first register and the elements 0, 2, 4, and 6 from the second register.

16. The method as recited in claim 15, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the second register;

the element 1 replicated from the element 2 of the second register;

the element 2 replicated from the element 4 of the second register;

the element 3 replicated from the element 6 of the second register;

the element 4 replicated from the element 0 of the first register;

the element 5 replicated from the element 2 of the first register;

the element 6 replicated from the element 4 of the first register; and

the element 7 replicated from the element 6 of the first register.

17. The method as recited in claim 11, wherein the subset is comprised of the elements 4, 5, 6, and 7 from the first register and the elements 4, 5, 6, and 7 from the second register.

18. The method as recited in claim 17, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 4 of the second register;

the element 1 replicated from the element 4 of the first register;

the element 2 replicated from the element 5 of the second register;

the element 3 replicated from the element 5 of the first register;

the element 4 replicated from the element 6 of the second register;

the element 5 replicated from the element 6 of the first register;

the element 6 replicated from the element 7 of the second register; and

the element 7 replicated from the element 7 of the first register.

19. The method as recited in claim 11, wherein the subset is comprised of the elements 0, 1, 2, and 3 from the first register and the elements 0, 1, 2, and 3 from the second register.

20. The method as recited in claim 19, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the second register;

the element 1 replicated from the element 0 of the first register;

the element 2 replicated from the element 1 of the second register;

the element 3 replicated from the element 1 of the first register;

the element 4 replicated from the element 2 of the second register;

the element 5 replicated from the element 2 of the first register;

the element 6 replicated from the element 3 of the second register; and

the element 7 replicated from the element 3 of the first register.

21. The method as recited in claim 11, wherein the subset is comprised of the elements 4, 5, 6, and 7 from the first register.

22. The method as recited in claim 21, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 4 of the first register;

the element 2 replicated from the element 5 of the first register;

the element 4 replicated from the element 6 of the first register;

the element 6 replicated from the element 7 of the first register; and

the elements 1, 3, 5, and 7 containing a zero in all the bits.

23. The method as recited in claim 11, wherein the subset is comprised of the elements 0, 1, 2, and 3 from the first register.

24. The method as recited in claim 23, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the first register;

the element 2 replicated from the element 1 of the first register;

the element 4 replicated from the element 2 of the first register;

the element 6 replicated from the element 3 of the first register; and

the elements 1, 3, 5, and 7 containing a zero in all the bits.

25. The method as recited in claim 11, wherein the subset is comprised of the elements 4, 5, 6, and 7 from the first register.

26. The method as recited in claim 25, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 4 of the first register;

the element 1 replicating the sign bit of the element 4 of the first register in all the bits;

the element 2 replicated from the element 5 of the first register;

the element 3 replicating the sign bit of the element 5 of the first register in all the bits;

the element 4 replicated from the element 6 of the first register;

the element 5 containing the sign bit of the element 6 of the first register in all the bits;

the element 6 replicated from the element 7 of the first register; and

the element 7 containing the sign bit of the element 7 of the first register in all the bits.

27. The method as recited in claim 11, wherein the subset is comprised of the elements 0, 1, 2, and 3 from the first register.

28. The method as recited in claim 27, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the first register;

the element 1 containing the sign bits of the element 0 of the first register;

the element 2 replicated from the element 1 of the first register;

the element 3 containing the sign bits of the element 1 of the first register;

the element 4 replicated from the element 2 of the first register;

the element 5 containing the sign bits of the element 2 of the first register;

the element 6 replicated from the element 3 of the first register; and

the element 7 containing the sign bits of the element 3 of the first register.

29. The method as recited in claim 10, wherein the subset is comprised of two elements from the first register and two elements from the second register.

30. The method as recited in claim 10, wherein the subset is comprised of the elements 0 and 2 from the first register and the elements 0 and 2 from the second register.

31. The method as recited in claim 30, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the second register;

the element 1 replicated from the element 2 of the second register;

the element 2 replicated from the element 0 of the first register; and

the element 3 replicated from the element 2 of the first register.

32. The method as recited in claim 10 further comprising the step of storing the elements in the third register to the memory unit.

33. The method as recited in claim 10, wherein the subset is comprised of the elements 0 and 1 from the first register and the elements 0 and 1 from the second register.

34. The method as recited in claim 33, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the second register;

the element 1 replicated from the element 0 of the first register;

the element 2 replicated from the element 1 of the second register; and

the element 3 replicated from the element 1 of the first register.

35. The method as recited in claim 10, wherein the subset is comprised of the elements 1 and 3 from the first register and the elements 1 and 3 from the second register.

36. The method as recited in claim 35, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 1 of the second register;

the element 1 replicated from the element 3 of the second register;

the element 2 replicated from the element 1 of the first register; and

the element 3 replicated from the element 3 of the first register.

37. The method as recited in claim 10, wherein the subset is comprised of the elements 0 and 2 from the first register and the elements 1 and 3 from the second register.

38. The method as recited in claim 37, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 1 of the second register;

the element 1 replicated from the element 0 of the first register;

the element 2 replicated from the element 3 of the second register; and

the element 3 replicated from the element 2 of the first register.

39. The method as recited in claim 10, wherein the subset is comprised of the elements 0 and 2 from the first register and the elements 1 and 3 from the second register.

40. The method as recited in claim 39, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 3 of the second register;

the element 1 replicated from the element 2 of the first register;

the element 2 replicated from the element 1 of the second register; and

the element 3 replicated from the element 0 of the first register.

41. The method as recited in claim 10, wherein the subset is comprised of the elements 2 and 3 from the first register and the elements 2 and 3 from the second register.

42. The method as recited in claim 41, wherein particular order of the elements in the third register comprises:

the element 0 replicated from the element 2 of the second register;

the element 1 replicated from the element 3 of the second register;

the element 2 replicated from the element 2 of the first register; and

the element 3 replicated from the element 3 of the first register.

43. The method as recited in claim 10, wherein the subset is comprised of the elements 0 and 2 from the first register and the elements 0 and 1 from the second register.

44. The method as recited in claim 43, wherein the particular order of the elements in the third register comprises:

the element 0 replicated from the element 0 of the second register;

the element 1 replicated from the element 1 of the second register;

the element 2 replicated from the element 0 of the first register; and

the element 3 replicated from the element 2 of the first register.