High speed MOS-technology power device integrated structure, and related manufacturing process

• US 5,933,734 A
• Filed: 03/04/1997
• Issued: 08/03/1999
• Est. Priority Date: 07/14/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Frisina, Ferruccio, Ferla, Giuseppe
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/813,009
• Time in Patent Office: 882 Days
• Field of Search: 438/268-281, 438/520, 438/525
• US Class Current: 438/268
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the insulated gate layer is lowered.

Claims

1. Process for the manufacturing of a high-speed MOS-technology power device integrated structure, comprising the steps of:

a) selectively implanting and thermally diffusing a heavy dose of a first dopant of a second conductivity type into a lightly doped semiconductor material layer of a first conductivity type to form a plurality of heavily doped deep body regions;

b) growing a thin oxide layer over a surface of the semiconductor material layer, and depositing a polysilicon layer over the thin oxide layer;

c) selectively removing the polysilicon layer and the thin oxide layer around each deep body region;

d) implanting and thermally diffusing a low dose of a second dopant of the second conductivity type using the polysilicon layer as a mask, to form channel regions, said channel regions extending under the thin oxide layer;

e) selectively implanting and thermally diffusing a heavy dose of a third dopant of the first conductivity type to form heavily doped source regions;

f) selectively removing from the polysilicon layer an oxide layer formed over the polysilicon layer and over the body regions during said thermal diffusion of the first, second and third dopants;

g) depositing over the whole surface a layer of a metallic element suitable to form, together with silicon, a silicide layer;

h) performing a thermal process to make the metallic element react with polysilicon to form a silicide layer over the polysilicon layer.

2. Process according to claim 1, wherein said metallic element is cobalt.

3. Process for the manufacturing of a high speed MOS-technology power device integrated structure, comprising the steps of:

a) growing a thin oxide layer over a surface of a lightly doped semiconductor material layer of a first conductivity type, depositing a polysilicon layer over the thin oxide layer, forming a silicide layer over the polysilicon layer, covering the silicide layer with an insulating material layer;

b) selectively removing the insulating material layer, the silicidc layer, the polysilicon layer and the thin oxide layer to form a plurality of windows defining respective uncovered surface areas of the semiconductor material layer;

c) implanting a high dose of a first donant of a second conductivity type along directions which are tilted of a first prescribed angle with respect to a direction orthogonal to a surface of the semiconductor material layer, said first angle depending on an overall thickness of the thin oxide layer, the polysilicon layer, the silicide layer and the insulating material layer to prevent the first dopant from being implanted in a central region of said uncovered surface areas, to form source regions of the first conductivity type;

d) implanting a low dose of a second dopant of the first conductivity type along directions tilted at a second prescribed angle with respect to said orthogonal direction, to form doped regions of the second conductivity type each comprising lightly doped channel regions extending under edges of the windows;

e) implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the windows.

4. Process according to claim 3, wherein said silicide layer is a cobalt silicide.

5. Process according to claim 3, wherein said first prescribed angle is chosen in the range of 45°

-60°

.

6. Process according to claim 3, wherein said second prescribed angle is chosen in the range of 35°

-60°

.

7. Process according to claim 3, wherein said windows have two elongated edges and two short edges, and in that:

said first dopant of the first conductivity type is implanted along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at said first prescribed angle with respect to an orthogonal direction to form pairs of heavily doped elongated source regions of the first conductivity type which extend along said two elongated edges of each elongated window and which are separated a central stripe;

said second dopant is implanted along two directions which lie in said plane, and which are substantially symmetrically tilted at said second prescribed angle with respect to said orthogonal direction, to form lightly doped elongated channel regions extending under the two elongated edges of each elongated window.