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High speed MOS-technology power device integrated structure, and related manufacturing process

  • US 5,933,734 A
  • Filed: 03/04/1997
  • Issued: 08/03/1999
  • Est. Priority Date: 07/14/1994
  • Status: Expired due to Term
First Claim
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1. Process for the manufacturing of a high-speed MOS-technology power device integrated structure, comprising the steps of:

  • a) selectively implanting and thermally diffusing a heavy dose of a first dopant of a second conductivity type into a lightly doped semiconductor material layer of a first conductivity type to form a plurality of heavily doped deep body regions;

    b) growing a thin oxide layer over a surface of the semiconductor material layer, and depositing a polysilicon layer over the thin oxide layer;

    c) selectively removing the polysilicon layer and the thin oxide layer around each deep body region;

    d) implanting and thermally diffusing a low dose of a second dopant of the second conductivity type using the polysilicon layer as a mask, to form channel regions, said channel regions extending under the thin oxide layer;

    e) selectively implanting and thermally diffusing a heavy dose of a third dopant of the first conductivity type to form heavily doped source regions;

    f) selectively removing from the polysilicon layer an oxide layer formed over the polysilicon layer and over the body regions during said thermal diffusion of the first, second and third dopants;

    g) depositing over the whole surface a layer of a metallic element suitable to form, together with silicon, a silicide layer;

    h) performing a thermal process to make the metallic element react with polysilicon to form a silicide layer over the polysilicon layer.

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