Shallow trench isolation process

• US 5,933,748 A
• Filed: 12/31/1996
• Issued: 08/03/1999
• Est. Priority Date: 01/22/1996
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, George, Chen, Coming
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US08/775,805
• Time in Patent Office: 945 Days
• Field of Search: 438/431, 438/437, 438/FOR 227, 438/702, 438/692, 438/693, 438/FOR 111, 438/959, 148/DIG. 85, 148/DIG. 86, 148/DIG. 50
• US Class Current: 438/431
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

A shallow trench isolation process provides a high quality oxide on the substrate adjacent the trench and on the upper part of the trench. This process avoids the formation of poor quality oxide on the substrate adjacent the upper edge of the trench that is believed to cause MOS transistors to exhibit the undesirable subthreshold current flow known as the "kink" effect. A pad oxide layer is grown on the surface of a silicon substrate and then a layer of silicon nitride is formed on the surface of the pad oxide. A photoresist mask is formed over the silicon nitride and the silicon nitride and pad oxide are etched, and then the substrate is etched to form a trench. The photoresist mask is removed, a layer of polysilicon is deposited over the silicon nitride layer and within the trench and the polysilicon layer is oxidized. CVD oxide is deposited to overfill the trench and then the excess CVD oxide and polysilicon oxide is removed by CMP, using the silicon nitride layer as an polish stop. The silicon nitride is stripped and the trench oxide is etched using an HF dip to provide a substantially planar surface. A layer of polysilicon is deposited on the device and doping, patterning and etching are used to define wiring lines and gate electrodes from the polysilicon. The polysilicon oxide lining the trench is more durable than the CVD oxide that fills the rest of the trench, and so better protects the substrate near the trench during subsequent etching and polishing steps.

Claims

1. A method of making a semiconductor device comprising the steps of:

providing a semiconductor substrate having a surface;

forming a mask over a trench region and etching through the surface of the semiconductor substrate to form a trench within the semiconductor substrate;

depositing a layer of polysilicon over the substrate and within the trench;

oxidizing the layer of polysilicon within the trench to form a layer of oxidized polysilicon that extends above the surface of the substrate adjacent to the trench;

filling the trench with an insulating material; and

forming a gate oxide layer over the surface of the substrate subsequent to the step of filling the trench with the insulating material, wherein the layer of oxidized polysilicon extends above the surface of the substrate adjacent to the trench subsequent to the step of forming a gate oxide layer.

2. The method of claim 1, wherein the insulating material is a TEOS oxide having an upper surface at or near the surface of the semiconductor substrate.

3. The method claim 2, wherein the entire layer of polysilicon is oxidized so that the layer of polysilicon oxide covers the surface of the device and the trench, the method further comprising the steps of:

removing a portion of the insulating material, leaving at least some of the insulating material within the trench; and

removing a portion of the layer of polysilicon oxide, while leaving at least some of the layer of polysilicon oxide within the trench.

4. The method of claim 3, further comprising the step of forming a layer of silicon nitride over the substrate prior to depositing the layer of polysilicon, wherein the steps of removing a portion of the insulating material and of removing a portion of the layer of polysilicon oxide are performed by a planarizing chemical mechanical polishing process using the layer of silicon nitride as a stop for the polishing process.

5. A method of making a semiconductor device comprising the steps of:

providing a semiconductor substrate having a surface;

forming a silicon nitride layer over the surface of the semiconductor substrate;

etching the silicon nitride layer to expose the surface of the semiconductor substrate and etching through the surface of the semiconductor substrate to form a trench within the semiconductor substrate;

depositing a layer of polysilicon over the silicon nitride layer and within the trench so that the layer of polysilicon is in contact with the semiconductor substrate within the trench near the surface of the substrate;

oxidizing the layer of polysilicon within the trench to form a layer of polysilicon oxide at least adjacent to the surface of the substrate;

forming an insulating plug within the trench and having a upper surface;

stripping the silicon nitride layer from a surface of a thermal oxide layer covering the surface of the substrate;

subsequently forming a layer of gate oxide over the surface of the substrate, a surface of the layer of gate oxide adjacent to the trench being lower than an upper edge of the layer of polysilicon oxide; and

forming a wiring line extending over a portion of the surface of the semiconductor substrate and extending onto or above the upper surface of the insulating plug.

6. The method of claim 5, wherein the wiring line is in contact with a gate oxide formed over the surface of the semiconductor substrate, with the layer of polysilicon oxide, and with the insulating plug.

7. The method of claim 5, wherein the insulating plug is formed by depositing a layer of oxide over the surface of the substrate and within the trench.

8. The method of claim 7, wherein the layer of oxide is deposited to overfill the trench and wherein an excess portion of the layer of oxide is removed using chemical mechanical polishing.

9. The method of claim 7, wherein the layer of silicon nitride functions as a stop for a chemical mechanical polishing process used to remove a portion of the insulating plug.

10. The method of claim 5, comprising the further step of depositing a layer of polysilicon on the gate oxide layer, on exposed edges of the layer of polysilicon oxide, and on the upper surface of the insulating plug.

11. A method of making a semiconductor device comprising the steps of:

providing a semiconductor substrate having a surface;

forming a mask over a trench region and etching through the surface of the semiconductor substrate to form a trench within the semiconductor substrate;

depositing a layer of polysilicon over the substrate and within the trench;

oxidizing the layer of polysilicon within the trench to form a layer of oxidized polysilicon that extends above the surface of the substrate adjacent to the trench;

filling the trench with an insulating material; and

forming a gate oxide layer over the surface of the substrate so as to abut a portion of the layer of oxidized polysilicon above the surface of the substrate adjacent to the trench, subsequent to the step of filling the trench with the insulating material.