Open-bottomed via liner structure and method for fabricating same

• US 5,933,753 A
• Filed: 12/16/1996
• Issued: 08/03/1999
• Est. Priority Date: 12/16/1996
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Simon, Andrew H., Uzoh, Cyprian E.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/767,572
• Time in Patent Office: 960 Days
• Field of Search: 437/192, 437/187, 438/626, 438/624, 438/635, 438/674, 438/653, 438/681, 438/687, 438/629, 438/637, 438/639, 438/648
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention relates to a method of forming a bottomless liner structure. The method involves the steps of first obtaining a material having a via. Next, a first layer is deposited on the material, the first layer covering the sidewalls and bottom of the via. Finally, a second layer is sputter deposited on the first material, the material Rf biased during at least a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

Claims

1. A method of forming a bottomless liner structure, comprising:

a) obtaining a material having a via;

b) depositing a first layer on the material having the via, the first layer covering the sidewalls and bottom of the via;

c) sputter depositing a second layer on the first layer, the material being Rf biased during a portion of the time that the second layer is sputter deposited, such that the first layer deposited on the bottom of the via is substantially removed and substantially all of the first layer deposited on the sidewalls of the via is unaffected.

2. The method according to claim 1 wherein the material is a substrate.

3. The method according to claim 1, wherein the first layer covering the via comprises an insulating material.

4. The method according to claim 1, wherein the first layer covering the via comprises a semiconducting material.

5. The method according to claim 1, wherein the first layer covering the via comprises a conducting material.

6. The method according to claim 5 wherein the first layer covering the via is selected from the group consisting of titanium, titanium nitride, tungsten, titanium tungsten, tungsten nitride, tantalum, TaN, TaN/Ta, Ta/TaN, and Ta/TaN/Ta.

7. The method according to claim 6 wherein the first layer is TaN/Ta.

8. The method according to claim 1 wherein the second layer is a metal.

9. The method according to claim 8 wherein the second layer is copper.

10. The method according to claim 1 wherein the sputter deposition Rf biasing is active for a minimum of about 25% and a maximum of about 50% of the total sputter deposition time.