Adaptive dual filter echo cancellation

• US 5,933,797 A
• Filed: 02/28/1997
• Issued: 08/03/1999
• Est. Priority Date: 02/28/1997
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Hammar, Claes, H.ang.akansson, Stefan, Trump, Tonu
• Primary Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/810,601
• Time in Patent Office: 886 Days
• Field of Search: 364/572, 364/724.19, 364/574, 364/724.13, 364/736.01, 379/3, 379/399, 379/406, 379/410, 320/282, 320/286, 320/289, 325/232, 455/570, 381/71.1, 348/607, 348/611, 702/107, 702/189, 702/190, 702/191
• US Class Current: 702/191
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers

Abstract

A digital signal processor that is used for echo cancellation computations is disclosed, which includes parallel multiplier/adders, an input signal sample memory, and a plurality of accumulators for temporarily storing the results of the computations performed. Consequently, not all of the computational results have to be saved in an external data memory, which minimizes data transfer bottlenecks and significantly increases the computational efficiency of the digital signal processor. The adaptive filter coefficient updates can thereby be computed much faster, and the adaptive filter coefficients can be copied much faster from one filter to the other. The computational complexity of the digital signal processor is significantly less than that of prior digital signal processors.

Claims

1. A dual filter echo canceller for cancelling echos in a telephony system, said dual filter echo canceller comprising:

an adaptive filter;

a fixed filter coupled to said adaptive filter; and

a digital signal processor configured to implement the adaptive filter and the fixed filter so as to process during one clock cycle an input signal sample within an adaptive dual filter echo cancellation algorithm including coefficient updating, filtering and coefficient copying between the adaptive filter and fixed filter, said digital signal processor further includes;

a sample memory for storing the input signal sample;

a plurality of multipliers, at least one input of each of said plurality of multipliers coupled to an output of said sample memory;

a plurality of adders, an output of each of said plurality of multipliers coupled to at least one of said plurality of adders; and

a plurality of temporary storage devices, an input and output of each of said plurality of temporary storage devices selectively coupled to at least one of said plurality of multipliers and said plurality of adders.

2. The dual filter echo canceller of claim 1, further comprising a plurality of data memory devices located in a core of said digital signal processor and used to store coefficients of the adaptive filter and the fixed filter.

3. The dual filter echo canceller of claim 1, further comprising a plurality of data memory devices located outside of a core of said digital signal processor and used to store coefficients of the adaptive filter and the fixed filter.

4. The dual filter echo canceller of claim 1, wherein said digital signal processor further includes a plurality of data memory devices, each of said plurality of data memory devices coupled to an input of at least one of said plurality of multipliers.

5. The dual filter echo canceller of claim 4, wherein each of said plurality of data memory devices is coupled to at least one of said plurality of temporary memory storage devices.

6. The dual filter echo canceller of claim 1, wherein said digital signal processor further includes an arithmetic logic unit, an input and output of said arithmetic logic unit selectively coupled to at least one of said plurality of temporary memory storage devices, said plurality of multipliers, and said plurality of adders.

7. The dual filter echo canceller of claim 6, wherein said digital signal processor further includes a barrel shifter and an arithmetic logic unit for performing calculations required by a control part of the adaptive dual filter echo cancellation algorithm, said barrel shifter and said arithmetic logic unit each connected to at least one of said plurality of temporary storage devices.

8. The dual filter echo canceller of claim 1, wherein each of said temporary memory storage devices comprises an accumulator.

9. The dual filter echo canceller of claim 1, wherein said plurality of multipliers further includes two multipliers.

10. The dual filter echo canceller of claim 1, wherein said plurality of adders further includes two adders.

11. The dual filter echo canceller of claim 1, wherein said plurality of temporary memory storage devices further includes four accumulators.

12. The dual filter echo canceller of claim 1, wherein said input signal sample further includes a speech signal of a far end talker.

13. The dual filter echo canceller of claim 1, wherein said telephony system further includes a selected one of a mobile services switching center and a mobile telephone.

14. A method for cancelling echos using an echo canceller including an adaptive filter and a fixed filter each implemented in a digital signal processor capable of processing during one clock cycle an adaptive dual filter echo cancellation algorithm for an input signal sample, said digital signal processor includes:

a sample memory for storing the input signal sample;

a plurality of multipliers, at least one input of each of said plurality of multipliers coupled to an output of said sample memory;

a plurality of adders, an output of each of said plurality of multipliers coupled to at least one of said plurality of adders; and

a plurality of temporary storage devices, an input and output of each of said plurality of temporary storage devices selectively coupled to at least one of said plurality of multipliers and said plurality of adders, said method comprising the steps of;

computing a first output signal from the adaptive filter;

responsive to the first output signal, updating a coefficient of the adaptive filter; and

copying the updated coefficient of the adaptive filter to the fixed filter;

or

copying a fixed coefficient of the fixed filter to the adaptive filter.

15. The method of claim 14, wherein said step of updating further includes the following steps:

storing a plurality of the input signal samples in the sample memory;

storing a constant multiplier value in a first storage location;

retrieving a first filter coefficient value from a first data memory location;

storing said first filter coefficient value in a first temporary storage location of the plurality of temporary storage devices;

retrieving a second filter coefficient value from a second data memory location;

storing said second filter coefficient value in a second temporary storage location of the plurality of temporary storage devices;

multiplying a first input signal sample of said plurality of input signal sample by said constant multiplier value; and

adding a product of said multiplying step to said first filter coefficient value, and storing a result of said adding step in said first temporary storage location.

16. The method of claim 15, further comprising the steps of:

retrieving a third filter coefficient value from a third data memory location;

storing said third filter coefficient value in a third temporary storage location of the plurality of temporary storage devices, and multiplying a second input signal sample of said plurality of input signal sample by said constant multiplier value; and

adding a product of said multiplying step to said second filter coefficient value, and storing a result of said adding step in said second temporary storage location.

17. The method of claim 16, further comprising the steps of:

retrieving a fourth filter coefficient value from a fourth data memory location;

storing said fourth filter coefficient value in a fourth temporary storage location of the plurality of temporary storage devices, and multiplying a third input signal sample of said plurality of input signal sample by said constant multiplier value;

adding a product of said multiplying step to said third filter coefficient value, and storing a result of said adding step in said third temporary storage location; and

storing said result from said first temporary storage location in said first data memory location.

18. The method of claim 17, wherein each of said first, second, third and fourth temporary storage locations further includes an accumulator.