Write through virtual cache memory, alias addressing, and cache flushes

• US 5,933,844 A
• Filed: 04/25/1994
• Issued: 08/03/1999
• Est. Priority Date: 11/04/1991
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Young, Mark
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/232,600
• Time in Patent Office: 1,926 Days
• Field of Search: 395/400, 395/425, 711/138, 711/139, 711/3, 711/210, 711/135, 711/203, 711/144, 711/142
• US Class Current: 711/3
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed

Abstract

In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.

Claims

1. In a computer system comprising a central processing unit (CPU) coupled to a cache memory and a main memory executing a plurality of processes, wherein cache hits/misses are based on virtual addresses and some of said virtual addresses are alias addresses to each other, a method for said CPU to update said cache and main memory that reduces cache flushings, said method comprising the steps of:

receiving by said cache memory a write signal and a virtual address from said CPU;

determining by said cache memory if said virtual address results in a selected one of a write cache hit and a write cache miss based on said virtual address and mapping by said cache memory said virtual address to a physical address that identifies a memory location of a memory block of said main memory;

providing by said cache memory a first control signal to an internal cache memory data array instructing said internal cache memory data array to accept a data byte from said CPU if said virtual address results in said write cache hit, said data byte being dispatched by said CPU to said cache memory, said data byte being cached in a cache line of said cache memory upon acceptance by said cache memory, said cache line being identified by said virtual address and corresponding to said memory block;

providing by said cache memory said physical address and a second control signal to said main memory, said second control signal instructing said main memory to accept said data byte from said CPU and storing said data byte in said memory location, said data byte being also dispatched by said CPU to said main memory;

determining by said cache memory if said main memory location identified by said physical address is a non-cacheable memory location of a non-cacheable memory block of said main memory; and

waiting by said cache memory for the result of said non-cacheability determination, the result of said non-cacheability determination being available after the result of said cache hit/miss determination, then without detecting for alias addresses of said virtual address, conditionally flushing by said cache memory a cache line in which said memory block could have been cached if said virtual address results in said write cache miss and said memory location is not a non-cacheable memory location.

2. The method as set forth in claim 1, wherein, said step of determining by said cache memory if said main memory location is a non-cacheable memory location of a non-cacheable memory block comprises checking by said cache memory if a "Do Not Cache" bit of a physical memory page descriptor in a physical memory page table of said cache memory for a physical memory page is set, said physical memory page comprising said memory block, said "Do Not Cache" bit being set by said cache memory if said physical memory page including said memory block is non-cacheable.

3. The method as set forth in claim 1, wherein, said step of flushing said cache line by said cache memory comprises unsetting by said cache memory a valid bit in a cache tag of said cache memory for said cache line, thereby invalidating data currently cached in said cache line, said valid bit being set by said cache memory if data currently cached in said cache line are valid.

4. In a computer system comprising a central processing unit (CPU) coupled to a cache memory and a main memory executing a plurality of processes, wherein cache hits/misses are based on virtual addresses and some of said virtual addresses are alias addresses to each other, a cache memory controller for said CPU to update said cache and main memory that reduces cache flushings, said cache memory controller comprising:

a cache tag array for storing a plurality of cache tags identifying a plurality of memory blocks of said main memory currently cached in a plurality of cache lines of said cache memory corresponding to said cache tags;

a memory management unit for mapping virtual addresses to physical addresses that identify memory locations of memory blocks of said main memory, and tracking non-cacheable physical memory pages of said main memory, said non-cacheable physical memory pages comprising non-cacheable memory blocks; and

a cache control logic coupled to said CPU, said cache tag array, and said memory management unit for receiving a write signal and a virtual address from said CPU, determining if said virtual address results in a selected one of a write cache hit and a write cache miss based on said virtual address and using said cache tag array, mapping said virtual address to a physical address that identifies a memory location of said main memory using said memory management unit, providing a first control signal to said cache memory instructing said cache memory to accept a data byte from said CPU if said virtual address results in said write cache hit, providing said physical address and a second write control signal to said main memory instructing said main memory to accept said data byte from said CPU and storing said data byte in said memory location, determining if said main memory location identified by said physical address is a non-cacheable memory location using also said memory management unit, and waiting for the result of said non-cacheability determination, the result of said non-cacheability determination being available after the result of said cache hit/miss determination, then without detecting for alias addresses of said virtual address, conditionally flushing a cache line in which said memory block could have been cached if said virtual address results in said write cache miss and said memory location is not a non-cacheable memory location;

said data byte being dispatched by said CPU to said main memory and said cache memory simultaneously, said data byte being cached in a cache line of said cache memory upon acceptance by said cache memory, said cache line being identified by said virtual address and corresponding to said memory block.

5. The apparatus as set forth in claim 4, wherein,

said memory management unit tracks non-cacheable physical memory pages of said main memory by setting a "Do Not Cache" bit in a physical memory page descriptor block in a physical memory page descriptor table for each non-cacheable physical memory page;

and

said cache control logic determines if said main memory location is a non-cacheable memory location by checking if said "Do Not Cache" bit of said physical memory page descriptor block for a physical memory page comprising said memory block is set.

6. The apparatus as set forth in claim 4, wherein, said cache control logic flushes said cache line by unsetting a valid bit in a cache tag for said cache line thereby invalidating data currently cached in said cache line, said valid bit being set by said cache control logic if data currently cached in said cache line are valid.

7. The computer system as set forth in claim 4 wherein said cache memory controller further comprises:

an alias control logic coupled to said cache control logic for detecting alias addresses when said CPU attempts to read from said cache memory.

8. An improved computer system comprising a central processing unit (CPU) coupled to a cache memory and a main memory executing a plurality of processes, wherein cache hits/misses are determined based on virtual addresses, some of said virtual addresses are alias addresses to each other, and cacheability of memory locations is determined as an integral part of virtual address to physical address translations, said improvement comprising an improved cache memory controller coupled to said CPU, said cache memory, and said main memory, that allows said CPU to update said cache and main memory with an improved write through with no write allocate approach that reduces cache flushes on write cache misses by waiting for the results of said cacheability determinations, the results of said cacheability determinations being available after the results of the corresponding cache hit/miss determinations, then without detecting for alias addresses of the virtual addresses, conditionally performing cache flushes for cache write misses only for cacheable memory locations.

9. The improved computer system as set forth in claim 8 wherein said cache memory controller further comprises:

an alias control logic coupled to said cache control logic for detecting alias addresses when said CPU attempts to read from said cache memory.