Computer system with a switch interconnector for computer devices

• US 5,935,233 A
• Filed: 05/21/1997
• Issued: 08/10/1999
• Est. Priority Date: 05/21/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Jeddeloh, Joseph
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US08/859,894
• Time in Patent Office: 811 Days
• Field of Search: 395/309, 395/310, 395/311, 395/308, 395/306, 395/280, 395/312, 711/118, 711/146, 710/126, 710/128, 710/129, 710/130, 710/131, 710/132, 710/100
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A computer bridge interconnects a plurality of computer buses. The computer bridge includes first and second bus interfaces structured for coupling to first and second computer buses, respectively. The computer bridge also includes a control switch having a request phase selector and a data phase selector connected to each of the first and second bus interfaces. The request phase selector selectively connects a second bus interface to the first bus interface during a request phase of a transaction. The data phase selector selectively connects the second bus interface to the first bus interface during a data phase of the transaction, thereby decoupling the data phase from the request phase. The switch may include dedicated connections between two pairs of computer buses so that data can be transmitted simultaneously between the two pairs of computer buses. As such, a transaction can be transmitted to or from any computer bus that is not currently transmitting or receiving a transaction without waiting for any internal bus of the computer bridge to become available.

Claims

1. A computer bridge for interconnecting at least three computer buses, comprising:

first, second, and third bus interfaces structured for coupling to first, second, and third computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface, the control switch including a request phase selector and a data phase selector each connected to the third bus interface, the request phase selector being structured to selectively connect each of the first and second bus interfaces to the third bus interface during request phases of transactions and the data phase selector being structured to selectively connect each of the first and second bus interfaces to the third bus interface during data phases of the transactions.

2. The computer bridge of claim 1 wherein the control switch further includes a request arbiter connected to the request phase selector and to the first and second bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and second bus interfaces and cause the request phase selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a transaction request that is selected by the request arbiter.

3. The computer bridge of claim 1 wherein the control switch is structured to selectively connect the first bus interface to the second bus interface.

4. A computer bridge for interconnecting at least three computer buses, comprising:

first, second, third, and fourth bus interfaces structured for coupling to first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface,

the control switch being structured to connect the first bus interface to the second bus interface while simultaneously connecting the third bus interface to the fourth bus interface.

5. The computer bridge of claim 4 wherein the control switch includes read and write pathways connecting the first bus interface to the third bus interface, the read pathway being structured to enable read data to be transmitted from the third bus interface to the first bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the first bus interface to the third bus interface.

6. The computer bridge of claim 4 wherein the control switch includes first, second, and third selectors connected to the first, second, and third bus interfaces, respectively, the first selector selectively connecting the second and third bus interfaces to the first bus interface, the second selector selectively connecting the first and third bus interfaces to the second bus interface, and the third selector selectively connecting the first and second bus interfaces to the third bus interface.

7. The computer bridge of claim 4 wherein the first bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the first computer bus and the master bus interface being structured to process transaction requests directed to the first computer bus.

8. A computer bridge for interconnecting at least three computer buses, comprising:

first, second, and third bus interfaces structured for coupling to first, second, and third computer buses, respectively;

a memory cache to which the third bus interface is connected; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface, the control switch including a snoop selector and a snoop arbiter each connected to the first and second bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and second bus interfaces and cause the snoop selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the third bus interface snooping the cache based on the selected snoop request.

9. A computer bridge for interconnecting a plurality of computer buses, comprising:

first and second bus interfaces structured for coupling to first and second computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first request phase selector and a first data phase selector each connected to the first bus interface, the first request phase selector being structured to selectively connect the second bus interface to the first bus interface during a request phase of a first transaction and the first data phase selector being structured to selectively connect the second bus interface to the first bus interface during a data phase of the first transaction, the control switch further including a request arbiter connected to the first request phase selector and to the second bus interface, the request arbiter being structured to determine whether the first bus interface is too busy to accept a transaction request from the second bus interface and cause the first request phase selector to connect the second bus interface to the first bus interface if the first bus interface is not too busy.

10. The computer bridge of claim 9 wherein the control switch includes a second request phase selector and a second data phase selector each connected to the second bus interface, the second request phase selector being structured to selectively connect the first bus interface to the second bus interface during a request phase of a second transaction and the data phase selector being structured to selectively connect the first bus interface to the second bus interface during a data phase of the second transaction.

11. The computer bridge of claim 9, further including a third bus interface coupled to a third computer bus wherein the control switch is structured to selectively connect the first and second bus interfaces to the third bus interface.

12. A computer bridge for interconnecting a plurality of computer buses, comprising:

first, second, third, and fourth bus interfaces structured for coupling to first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first request phase selector and a first data phase selector each connected to the first bus interface, the first request phase selector being structured to selectively connect the second bus interface to the first bus interface during a request phase of a first transaction and the first data phase selector being structured to selectively connect the second bus interface to the first bus interface during a data phase of the first transaction, the control switch being structured to connect the first bus interface to the second bus interface while simultaneously connecting the third bus interface to the fourth bus interface.

13. The computer bridge of claim 12 wherein the control switch includes read and write pathways connecting the first bus interface to the second bus interface, the read pathway being structured to enable read data to be transmitted from the first bus interface to the second bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the second bus interface to the first bus interface.

14. The computer bridge of claim 12 wherein the second bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the second computer bus and the master bus interface being structured to process transaction requests directed to the second computer bus.

15. A computer bridge for interconnecting a plurality of computer buses, comprising:

first, second, and third bus interfaces structured for coupling to first, second, and third computer buses, respectively, the third bus interface being coupled to a memory cache; and

a control switch coupled to each of the bus interfaces, the control switch including a first request phase selector and a first data phase selector each connected to the first bus interface, the first request phase selector being structured to selectively connect the second bus interface to the first bus interface during a request phase of a first transaction and the first data phase selector being structured to selectively connect the second bus interface to the first bus interface during a data phase of the first transaction, the control switch including a snoop selector and a snoop arbiter each connected to the first and second bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and second bus interfaces and cause the snoop selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the third bus interface snooping the cache based on the selected snoop request.

16. A computer bridge for interconnecting at least four computer buses, comprising:

first, second, third, and fourth bus interfaces structured for coupling to first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first pathway connecting the first bus interface to the second bus interface and a second pathway connecting the third bus interface to the fourth bus interface while the first bus interface is connected to the second bus interface by the first pathway, the control switch further comprising;

a first request phase selector structured to selectively connect the first bus interface to the second bus interface during a request phase of a first transaction;

a first data phase selector structured to selectively connect the first bus interface to the second bus interface during a data phase of the first transaction;

a second request phase selector structured to selectively connect the third bus interface to the fourth bus interface during a request phase of a second transaction; and

a second data phase selector structured to selectively connect the third bus interface to the fourth bus interface during a data phase of the second transaction.

17. A computer bridge for interconnecting at least four computer buses, comprising:

first, second, third, and fourth bus interfaces structured for coupling to first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first pathway connecting the first bus interface to the second bus interface and a second pathway connecting the third bus interface to the fourth bus interface while the first bus interface is connected to the second bus interface by the first pathway, the control switch further comprising;

a first request arbiter connected to the first request phase selector and to the first and third bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and third bus interfaces and cause the first request phase selector to connect to the second bus interface whichever one of the first and third bus interfaces transmitted a transaction request that is selected by the first request arbiter; and

a second request arbiter connected to the second request phase selector and to the first and third bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and third bus interfaces and cause the second request phase selector to connect to the fourth bus interface whichever one of the first and third bus interfaces transmitted a transaction request that is selected by the second request arbiter.

18. The computer bridge of claim 17 wherein the control switch further includes first and second selectors connected to the second and fourth bus interfaces, respectively, the first selector being structured to selectively connect the first and third bus interfaces to the second bus interface and the second selector being structured to selectively connect the first and third bus interfaces to the fourth bus interface.

19. The computer bridge of claim 18 wherein the control switch further includes third and fourth selectors connected to the first and third bus interfaces, respectively, the third selector being structured to selectively connect the second and fourth bus interfaces to the first bus interface and the fourth selector being structured to selectively connect the second and fourth bus interfaces to the third bus interface.

20. The computer bridge of claim 17 wherein the first pathway of the control switch includes read and write pathways connecting the first bus interface to the second bus interface, the read pathway being structured to enable read data to be transmitted from the second bus interface to the first bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the first bus interface to the second bus interface.

21. The computer bridge of claim 17 wherein the first bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the first computer bus and the master bus interface being structured to process transaction requests directed to the first computer bus.

22. A computer bridge for interconnecting at least four computer buses, comprising:

first, second, third, and fourth bus interfaces structured for coupling to first, second, third, and fourth computer buses, respectively, the second bus interface being connected to a cache; and

a control switch coupled to each of the bus interfaces, the control switch including a first pathway connecting the first bus interface to the second bus interface and a second pathway connecting the third bus interface to the fourth bus interface while the first bus interface is connected to the second bus interface by the first pathway, the control switch including a snoop selector and a snoop arbiter each connected to the first and third bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and third bus interfaces and cause the snoop selector to connect to the second bus interface whichever one of the first and third bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the second bus interface snooping the cache based on the selected snoop request.

23. The computer bridge of claim 22 wherein the first bus interface is a processor interface coupled to a processor bus, the second bus interface is a first expansion bus interface coupled to a first expansion bus, the third bus interface is a second expansion bus interface coupled to a second expansion bus, and the fourth bus interface is a memory interface coupled to a system memory bus.

24. A computer system, comprising:

first, second, and third computer buses for implementing computer transactions;

first, second, and third bus interfaces coupled to the first, second, and third computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface, the control switch further including a request arbiter connected to the request phase selector and to the first and second bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and second bus interfaces and cause the request phase selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a transaction request that is selected by the request arbiter.

25. A computer system, comprising:

first, second, third, and fourth computer buses for implementing computer transactions;

first, second, third, and fourth bus interfaces coupled to the first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface,

the control switch being structured to connect the first bus interface to the second bus interface while simultaneously connecting the first bus interface to the third bus interface.

26. The computer system of claim 25 wherein the first computer bus is a processor bus, the second computer bus is an expansion bus, and the third computer bus is a system memory bus.

27. The computer system of claim 25 wherein the control switch includes read and write pathways connecting the first bus interface to the third bus interface, the read pathway being structured to enable read data to be transmitted from the third bus interface to the first bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the first bus interface to the third bus interface.

28. The computer system of claim 25 wherein the control switch includes first, second, and third selectors connected to the first, second, and third bus interfaces, respectively, the first selector selectively connecting the second and third bus interfaces to the first bus interface, the second selector selectively connecting the first and third bus interfaces to the second bus interface, and the third selector selectively connecting the first and second bus interfaces to the third bus interface.

29. The computer system of claim 27 wherein the first bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the first computer bus and the master bus interface being structured to process transaction requests directed to the first computer bus.

30. A computer system, comprising:

first, second, and third computer buses for implementing computer transactions;

first, second, and third bus interfaces coupled to the first, second, and third computer buses, respectively, the third bus interface being connected to a cache; and

a control switch coupled to each of the bus interfaces, the control switch being structured to selectively connect each of the first and second bus interfaces to the third bus interface, the control switch including a snoop selector and a snoop arbiter each connected to the first and second bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and second bus interfaces and cause the snoop selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the third bus interface snooping the cache based on the selected snoop request.

31. A computer system, comprising:

first and second computer buses for implementing computer transactions;

first and second bus interfaces coupled to the first and second computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first request phase selector and a first data phase selector each connected to the first bus interface, the first request phase selector being structured to selectively connect the second bus interface to the first bus interface during a request phase of a first transaction and the first data phase selector being structured to selectively connect the second bus interface to the first bus interface during a data phase of the first transaction, the control switch including a second request phase selector and a second data phase selector each connected to the second bus interface, the second request phase selector being structured to selectively connect the first bus interface to the second bus interface during a request phase of a second transaction and the data phase selector being structured to selectively connect the first bus interface to the second bus interface during a data phase of the second transaction.

32. The computer system of claim 31, further comprising a third bus interface coupled to a third computer bus wherein the control switch is structured to selectively connect the first and second bus interfaces to the third bus interface.

33. The computer system of claim 31, further comprising:

third and fourth computer buses for implementing computer transactions; and

third and fourth bus interfaces coupled to the third and fourth computer buses, respectively, wherein the control switch is structured to connect the first bus interface to the second bus interface while simultaneously connecting the first bus interface to a third bus interface coupled to a third computer bus.

34. The computer system of claim 33 wherein the control switch includes read and write pathways connecting the first bus interface to the second bus interface, the read pathway being structured to enable read data to be transmitted from the first bus interface to the second bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the second bus interface to the first bus interface.

35. The computer system of claim 33 wherein the second bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the second computer bus and the master bus interface being structured to process transaction requests directed to the second computer bus.

36. The computer system of claim 33, further comprising a third bus interface coupled to a cache, wherein the control switch includes a snoop selector and a snoop arbiter each connected to the first and second bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and second bus interfaces and cause the snoop selector to connect to the third bus interface whichever one of the first and second bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the third bus interface snooping the cache based on the selected snoop request.

37. A computer system, comprising:

first, second, third, and fourth computer buses for implementing computer transactions;

first, second, third, and fourth bus interfaces coupled to the first, second, third, and fourth computer buses, respectively; and

a control switch coupled to each of the bus interfaces, the control switch including a first pathway connecting the first bus interface to the second bus interface and a second pathway connecting the third bus interface to the fourth bus interface while the first bus interface is connected to the second bus interface by the first path, the control switch further comprising;

a first request phase selector structured to selectively connect the first bus interface to the second bus interface during a request phase of a first transaction;

a first data phase selector structured to selectively connect the first bus interface to the second bus interface during a data phase of the first transaction;

a second request phase selector structured to selectively connect the third bus interface to the fourth bus interface during a request phase of a second transaction;

a second data phase selector structured to selectively connect the third bus interface to the fourth bus interface during a data phase of the second transaction,

a first request arbiter connected to the first request phase selector and to the first and third bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and third bus interfaces and cause the first request phase selector to connect to the second bus interface whichever one of the first and third bus interfaces transmitted a transaction request that is selected by the first request arbiter; and

a second request arbiter connected to the second request phase selector and to the first and third bus interfaces, the request arbiter being structured to arbitrate between transaction requests received from the first and third bus interfaces and cause the second request phase selector to connect to the fourth bus interface whichever one of the first and third bus interfaces transmitted a transaction request that is selected by the second request arbiter.

38. The computer system of claim 37 wherein the control switch further includes first and second selectors connected to the second and fourth bus interfaces, respectively, the first selector being structured to selectively connect the first and third bus interfaces to the second bus interface and the second selector being structured to selectively connect the first and third bus interfaces to the fourth bus interface.

39. The computer system of claim 38 wherein the control switch further includes third and fourth selectors connected to the first and third bus interfaces, respectively, the third selector being structured to selectively connect the second and fourth bus interfaces to the first bus interface and the fourth selector being structured to selectively connect the second and fourth bus interfaces to the third bus interface.

40. The computer system of claim 37 wherein the first pathway of the control switch includes read and write pathways connecting the first bus interface to the second bus interface, the read pathway being structured to enable read data to be transmitted from the second bus interface to the first bus interface and the write pathway being separate from the read pathway and structured to enable write data to be transmitted from the first bus interface to the second bus interface.

41. The computer system of claim 37 wherein the first bus interface includes a target bus interface and a master bus interface, the target bus interface being structured to process transaction requests received from the first computer bus and the master bus interface being structured to process transaction requests directed to the first computer bus.

42. The computer system of claim 37 wherein the second bus interface is connected to a cache and the control switch includes a snoop selector and a snoop arbiter each connected to the first and third bus interfaces, the snoop arbiter being structured to arbitrate between snoop requests received from the first and third bus interfaces and cause the snoop selector to connect to the second bus interface whichever one of the first and third bus interfaces transmitted a snoop request that is selected by the snoop arbiter, the second bus interface snooping the cache based on the selected snoop request.

43. The computer system of claim 37 wherein the first computer bus is a computer processor, the second computer bus is a first expansion bus, the third computer bus is a second expansion bus, and the fourth computer bus is a system memory.