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Multiple global pattern history tables for branch prediction in a microprocessor

  • US 5,935,241 A
  • Filed: 12/10/1997
  • Issued: 08/10/1999
  • Est. Priority Date: 12/10/1996
  • Status: Expired due to Term
First Claim
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1. A microprocessor, comprising:

  • an execution unit for executing instructions according to a plurality of program types;

    a memory for storing instruction codes of instructions; and

    a fetch unit, for addressing the memory to retrieve instruction codes for execution by the execution unit, comprising;

    a branch history circuit, for storing a sequence of results of branching instructions executed by the execution unit;

    a plurality of pattern history tables coupled to the branch history circuit, each having a plurality of indexed prediction code entries, and each having an output for presenting the contents of one of the prediction code entries corresponding to a branch history field from the branch history circuit;

    an addressing circuit for selecting an address for an instruction to be fetched; and

    select logic, coupled to receive a program type indicator, for selectively forwarding, to the addressing circuit, the output of one of the plurality of pattern history tables corresponding to the program type indicator.

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