Multiple global pattern history tables for branch prediction in a microprocessor
First Claim
1. A microprocessor, comprising:
- an execution unit for executing instructions according to a plurality of program types;
a memory for storing instruction codes of instructions; and
a fetch unit, for addressing the memory to retrieve instruction codes for execution by the execution unit, comprising;
a branch history circuit, for storing a sequence of results of branching instructions executed by the execution unit;
a plurality of pattern history tables coupled to the branch history circuit, each having a plurality of indexed prediction code entries, and each having an output for presenting the contents of one of the prediction code entries corresponding to a branch history field from the branch history circuit;
an addressing circuit for selecting an address for an instruction to be fetched; and
select logic, coupled to receive a program type indicator, for selectively forwarding, to the addressing circuit, the output of one of the plurality of pattern history tables corresponding to the program type indicator.
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Accused Products
Abstract
A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction. A range register unit (75) for determining whether the instruction is contained within an address range is also disclosed as used in the selection of the pattern history table (53).
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Citations
24 Claims
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1. A microprocessor, comprising:
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an execution unit for executing instructions according to a plurality of program types; a memory for storing instruction codes of instructions; and a fetch unit, for addressing the memory to retrieve instruction codes for execution by the execution unit, comprising; a branch history circuit, for storing a sequence of results of branching instructions executed by the execution unit; a plurality of pattern history tables coupled to the branch history circuit, each having a plurality of indexed prediction code entries, and each having an output for presenting the contents of one of the prediction code entries corresponding to a branch history field from the branch history circuit; an addressing circuit for selecting an address for an instruction to be fetched; and select logic, coupled to receive a program type indicator, for selectively forwarding, to the addressing circuit, the output of one of the plurality of pattern history tables corresponding to the program type indicator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of operating a pipelined microprocessor to speculatively execute branching instructions in a program of microprocessor instructions, comprising the steps of:
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detecting a branch instruction at a fetch stage of the pipelined microprocessor; responsive to the detecting step, retrieving at least a portion of a branch history field; determining a program type corresponding to the branch instruction; and generating a branch prediction corresponding to the retrieved portion of the branch history field from one of a plurality of pattern history tables selected according to the program type. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification