Method and apparatus for memory array compressed data testing

• US 5,935,263 A
• Filed: 07/01/1997
• Issued: 08/10/1999
• Est. Priority Date: 07/01/1997
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Keeth, Brent, Martin, Chris G., Ryan, Kevin J., Manning, Troy A., Lee, Terry R., Voshell, Thomas W., Pearson, Mike, Fister, Wallace E., Pierce, Kim M.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/886,195
• Time in Patent Office: 770 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.4, 371/21.6, 365/189.05, 365/190, 365/208, 324/158 R
• US Class Current: 714/718
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: H03M 13/093 CRC update after modification of the information word

Abstract

A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Claims

1. A method of testing a memory device including a memory array, comprising:

writing data to the memory array in a predetermined pattern;

reading data from the array;

determining whether the read data are correct by comparing a plurality of the read data to a selected pattern;

if the read data match the selected pattern, supplying output data to a data bus over an output interval; and

if the read data do not match the selected pattern, providing an error indicator to the data bus during the output interval instead of providing the output data to the data bus.

2. The method of claim 1 wherein the memory device is a synchronous device responsive to a clock signal and wherein the step of supplying the output data over an output interval of the step of providing an error indicator to the data bus extends over a plurality of transitions of the clock signal.

3. The method of claim 2 wherein the number of transitions in the plurality of transitions of the clock signal equals the number of data bits in the plurality of read data that are compared to the selected pattern.

4. The method of claim 1, further including the step of storing the read data in respective registers and wherein the step of determining whether the read data are correct by comparing a plurality of the read data to a selected pattern includes comparing the stored data to the selected pattern.

5. The method of claim 1 wherein the error indicator is a tri-state output.

6. The method of claim 5, further including the step of producing an error indication with a test head in response to the tri-state output.

7. A method of transferring data from a memory array within a memory device to a data bus, comprising:

reading a plurality of data from the memory array;

determining, within the memory device, if any of the read data correspond to an error;

if any of the read data correspond to an error, producing a flag signal having a first logic state indicating the presence of an error and a second logic state indicating the absence of an error;

transferring the flag signal to an output driver circuit;

if the flag signal has the second logic state, outputting the read data from the output driver circuit during an output interval; and

if the flag signal has the first logic state producing an error indicator from the output driver circuit during the output interval.

8. The method of claim 7 wherein the step of transferring the signals corresponding to the read data includes sequentially providing the signals responsive to transitions of a clock signal, further including the step of sustaining the error indicator for a plurality of transitions of the clock signal.

9. The method of claim 7 wherein the step of producing an error indicator includes the step of producing a single error indicator corresponding to all of the bits in the group.

10. The method of claim 7 wherein the step of producing an error indicator includes producing a tri-state condition with the buffer.

11. The method of claim 7 wherein the step of determining if any of the read data correspond to an error includes the step of comparing the read data to a set of desired data.

12. A method of transferring data from a memory array to a data bus, comprising:

segmenting the data from the array into groups, each group containing a plurality of bits;

if any of the bits in a selected one of the groups corresponds to an error at the memory array, selectively blocking the selected group of data from the data bus; and

if none of the bits in the selected one of the groups corresponds to an error at the memory array, transferring the group of data to the data bus.

13. The method of claim 12 wherein the memory device is a synchronous device responsive to a clock signal and wherein the step of selectively blocking the group of data from the data bus includes blocking the group for a plurality of clock cycles.

14. The method of claim 12, further including reading the data from the array at a plurality of clock ticks.

15. The method of claim 14 wherein the step of separating the data into groups includes segmenting data from a plurality of clock ticks into each group.

16. The method of claim 15 wherein the step of blocking signals from the data bus includes blocking the signals for more than one clock tick.

17. The method of claim 13 wherein the step of determining if any of the read data correspond to an error includes the step of comparing the read data to a set of desired data.

18. The method of claim 12 wherein the step of supplying the group of data to the data bus includes sequentially providing the data in the group of data to an output driver.

19. The method of claim 12, further including the step of comparing the stored data to a selected bit pattern to determine if one of the bits in the read data corresponds to an error.

20. The method of claim 19 wherein transferring the group of data to the data bus includes inputting the stored data to an output driver.

21. The method of claim 20 wherein the step of blocking the group of data from the data bus includes the step of, if the data in the registers does not match the selected bit pattern, producing an error signal indicating that the read data are in error and wherein the step of selectively blocking the selected group of data from the data bus includes applying the error signal to the output driver to override the selected group of data bits.

22. The method of claim 21 wherein the step of applying the error signal to the output driver includes blocking a plurality of bits in the selected group of data.

23. The method of claim 22 wherein the step of applying the error bit includes blocking the entire selected group of data from the data bus.

24. A method of testing a memory device responsive to a clock signal, the memory device including a memory array comprising the steps of:

writing data to the memory array in a predetermined pattern;

after writing data to the memory array issuing a read command on a first clock transition;

at a second clock transition and responsive to the read command reading data from the memory array;

within the memory device comparing the data read from the memory array to the predetermined pattern;

producing an output signal responsive to the step of comparing the data read from the memory array to the predetermined pattern; and

at a plurality of clock transitions outputting the output signal from the memory device.

25. The method of claim 24 wherein the step of producing an output signal includes the steps of:

if the data read from the memory array match the predetermined pattern, outputting data corresponding to the read data; and

if the data read from the memory array does not match the predetermined pattern, outputting an error indicator.

26. The method of claim 25 wherein the step of outputting an error indicator includes producing an open circuit output signal.

27. A memory device, comprising:

an output driver circuit having a data output terminal adapted for coupling to a data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal in response to an error signal at the error input terminal;

a memory array arranged in rows and columns;

an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells within the memory array, the I/O interface including a plurality of output terminals;

a data path coupled between the I/O interface and the output driver circuit; and

a comparing circuit having an input coupled to the data path and an error output terminal coupled to the error input terminal, the comparing circuit being responsive to compare data on the data path to a selected set of data and to produce the error signal at the error output terminal in response to the data on the data path not matching the selected set of data.

28. The memory device of claim 27, further comprising a multiplexer coupled between the I/O interface and the data path.

29. The memory device of claim 27, further comprising a plurality of data registers coupled between each of the data paths and the output driver circuit.

30. The memory device of claim 29 wherein the data registers are serially coupled.

31. The memory device of claim 29, further comprising a multiplexer coupled between a first plurality of the data paths and a first of the registers.

32. A test system including:

a data bus;

a memory device including;

an output driver circuit having a data output terminal coupled to the data bus, an error input terminal and a data input terminal, the output driver circuit being operative to produce a tri-state output signal at the data output terminal in response to an error signal at the error input terminal;

a memory array arranged in rows and columns;

an I/O interface coupled to the array, the I/O interface being configured to read data from a plurality of memory cells within the memory array, the I/O interface including a plurality of output terminals;

a data path coupled between the I/O interface and the output driver circuit; and

a comparing circuit having an input coupled to the data path and an error output terminal coupled to the error input terminal, the comparing circuit being responsive to compare data on the data path to a selected set of data and to produce the error signal at the error output terminal in response to the data on the data path not matching the selected set of data;

a test head adapted for coupling to the output driver circuit, the test head being responsive to detect the tri-state condition; and

testing circuitry coupled to the test head.

33. The test system of claim 32 wherein the memory device further comprises a multiplexer coupled between the I/O interface and the data paths.

34. The test system of claim 32 wherein the memory device further comprises a plurality of data registers coupled between each of the data paths and the output driver circuit.

35. The test system of claim 34 wherein the data registers are serially coupled.

36. The test system of claim 32 wherein the comparing circuit is configured to compare a plurality of read data to a select pattern of read data to identify the error condition.