Method for powering-up a microprocessor under debugger control

• US 5,935,266 A
• Filed: 11/15/1996
• Issued: 08/10/1999
• Est. Priority Date: 11/15/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Whalen, Shaun P., Thurnhofer, Stefan
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/746,727
• Time in Patent Office: 998 Days
• Field of Search: 371/22.3, 371/22.1, 371/22.5, 395/183.06, 395/183.12, 395/183.15, 395/800, 364/579, 364/550, 324/512, 714/726, 714/23, 714/25, 714/27, 714/30, 714/36, 714/39, 714/47, 714/727, 714/733
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins. Next, the debugger controls the microprocessor via the data register of the JTAG interface, conducting the necessary functions pursuant to power-up. Once the power-up functions are performed and the reset signal is disasserted, the internal logic can be reconnected with the I/O connection pins by returning the BSR to its normal mode.

Claims

1. A method of powering-up a microprocessor in a system having an external controller, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, and a boundary scan interface including a boundary scan register (BSR), and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection meams in said test mode, said method comprising:

detecting when power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it; and

controlling said microprocessor with said external controller via said design-specific test data register while said BSR remains in said test mode.

2. The method of claim 1, wherein said boundary scan interface complies with IEEE 1149.1 standard (JTAG interface).

3. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic, a logic reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR), and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:

detecting when power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it;

setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state.

4. The method of claim 3, wherein said boundary scan interface complies with IEEE 1149.1 standard (JTAG interface).

5. The method of claim 4, said method further comprising:

reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.

6. The method of claim 5, wherein said reset condition is imposed by a reset signal, said method further comprising:

determining if said reset signal is cleared before reconnecting said internal logic with said I/O connection means.

7. The method of claim 6, wherein said reset signal is determined to be cleared by using said EXTEST JTAG instruction, said EXTEST JTAG instruction enabling said BSR to test said RESET signal.

9. The method of claim 5, wherein said microprocessor is connected to at least one system component, and wherein isolating said microprocessor further comprises

initializing said I/O connection means to deactivate said microprocessor relative to said system component.

10. The method of claim 9, wherein initializing said I/O connection means involves:

preloading said BSR with suitable pin values, said suitable pin values effecting a reset condition on said system component.

11. The method of claim 5, wherein setting said microprocessor to said debug state involves writing a particular value in a test data register of said microprocessor.

12. The method of claim 5, wherein said microprocessor executes said certain commands from a debug monitor when in said debug state.

13. The method of claim 12, wherein said debug monitor is resident in on-chip ROM.

14. The method of claim 12, wherein certain commands are sent by said debugger via said data register.

15. The method of claim 5, wherein reconnecting said internal logic from said I/O connection means includes loading a normal mode JTAG instruction into said instruction register.

16. The method of claim 15, wherein said normal mode JTAG instruction is SAMPLE/PRELOAD.

8. An external controller for controlling the power-up of a microprocessor, wherein said microprocessor is interconnected to at least on e system component, said microprocessor comprising I/O connection means, internal logic having a reset condition occurring when the power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR) and a least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said external controller comprising:

means for detecting when power is applied to said microprocessor;

means for isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it, wherein said means for isolating said microprocessor further comprises;

means for initializing said I/O connection means to deactivate said microprocessor relative to said system component;

means for setting said microprocessor to a debug state while said BSR is in said test mode;

means for instructing said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state;

means for reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.

17. An external controller for controlling the power-up of a microprocessor, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said external controller comprising:

means for detecting when power is applied to said microprocessor;

means for isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it;

means for setting said microprocessor to a debug state while said BSR is in said test mode;

means for instructing said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and

means for reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.

18. The external controller of claim 17, wherein said boundary scan interface complies with IEEE 1149.1 (JTAG interface).

19. The external controller of claim 18, wherein said system includes a boundary scan master (BSM) operatively connected to said JTAG interface and responsive to said debugger, said JTAG interface includes a device identification (ID) register, and wherein said means for detecting when said power is applied comprises:

means for instructing said JTAG interface to conduct an ID register scan of said microprocessor, said debugger detecting power to said microprocessor when said BSM receives valid device identification values.

20. A debugger control for controlling the power-up of a microprocessor in a system, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said debugger control comprising instructional means for:

detecting if power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition;

setting said microprocessor to a debug state;

delivering instructions to said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and

reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.

21. The debugger control of claim 20, wherein said boundary scan interface complies with IEEE 1149.1 (JTAG interface).

22. The debugger control of claim 21, wherein said system includes a boundary scan master (BSM) operatively connected to said JTAG interface and responsive to said debugger, said JTAG interface includes a device identification (ID) register, and wherein said instruction means for detecting when said power is applied comprises:

instructional means for conducting an ID register scan of said microprocessor using said JTAG interface, said power being detected when BSM receives valid device identification values.

23. In a microprocessor having I/O connection means, internal logic and an IEEE 1149.1 (JTAG) complaint interface including a boundary scan register (BSR), said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, the improvement comprising:

at least one design-specific test data register adapted to receive JTAG instructions from an external controller;

on-chip ROM containing a debug monitor;

at least a debug state wherein said internal logic fetches instructions from a debug monitor and executes commands in said debug monitor in response to at least one test mode JTAG instruction received in said design-specific test data register; and

means for switching said internal logic said debug state.

24. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic having a logic reset condition occurring when power is applied to said microprocessor, and a JTAG boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:

detecting when power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it;

setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state;

reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode;

wherein said system includes a boundary scan master (BSM) operatively connected to said JTAG interface and responsive to said debugger, said JTAG interface includes a device identification (ID) register; and

wherein detecting when said power is applied comprises;

activating said debugger prior to applying power to said microprocessor, said debugger instructing said JTAG interface to conduct an ID register scan of said microprocessor, said debugger detecting power to said microprocessor when BSM receives valid device identification values.

25. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic having a logic reset condition occurring when power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR), at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:

detecting when power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it, wherein isolating said internal logic from said I/O connection means includes loading a test mode JTAG instruction into said instruction register;

setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state; and

reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.

26. The method of claim 25, wherein said test mode JTAG instruction is EXTEST.

27. A debugger control for controlling the power-up of a microprocessor in a system, wherein said microprocessor is interconnected to at least one system component, said microprocessor comprising I/O connection means, internal logic having a reset condition occurring when power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said debugger control comprising instructional means for:

detecting if power is applied to said microprocessor;

isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition, wherein said instructional means for isolating said microprocessor further comprises;

instructional means for initializing said I/O connection means to deactivate said microprocessor relative to said system component;

setting said microprocessor to a debug state;

delivering JTAG instructions to said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and

reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.