Method for powering-up a microprocessor under debugger control
First Claim
1. A method of powering-up a microprocessor in a system having an external controller, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, and a boundary scan interface including a boundary scan register (BSR), and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection meams in said test mode, said method comprising:
- detecting when power is applied to said microprocessor;
isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it; and
controlling said microprocessor with said external controller via said design-specific test data register while said BSR remains in said test mode.
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Accused Products
Abstract
A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins. Next, the debugger controls the microprocessor via the data register of the JTAG interface, conducting the necessary functions pursuant to power-up. Once the power-up functions are performed and the reset signal is disasserted, the internal logic can be reconnected with the I/O connection pins by returning the BSR to its normal mode.
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Citations
27 Claims
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1. A method of powering-up a microprocessor in a system having an external controller, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, and a boundary scan interface including a boundary scan register (BSR), and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection meams in said test mode, said method comprising:
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detecting when power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it; and controlling said microprocessor with said external controller via said design-specific test data register while said BSR remains in said test mode. - View Dependent Claims (2)
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3. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic, a logic reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR), and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:
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detecting when power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it; setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state. - View Dependent Claims (4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16)
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8. An external controller for controlling the power-up of a microprocessor, wherein said microprocessor is interconnected to at least on e system component, said microprocessor comprising I/O connection means, internal logic having a reset condition occurring when the power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR) and a least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said external controller comprising:
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means for detecting when power is applied to said microprocessor; means for isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it, wherein said means for isolating said microprocessor further comprises; means for initializing said I/O connection means to deactivate said microprocessor relative to said system component; means for setting said microprocessor to a debug state while said BSR is in said test mode; means for instructing said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; means for reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.
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17. An external controller for controlling the power-up of a microprocessor, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said external controller comprising:
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means for detecting when power is applied to said microprocessor; means for isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition after having power applied to it; means for setting said microprocessor to a debug state while said BSR is in said test mode; means for instructing said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and means for reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode. - View Dependent Claims (18, 19)
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20. A debugger control for controlling the power-up of a microprocessor in a system, said microprocessor comprising I/O connection means, internal logic, a reset condition occurring when power is applied to said microprocessor, a debug state, and a boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said debugger control comprising instructional means for:
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detecting if power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition; setting said microprocessor to a debug state; delivering instructions to said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode. - View Dependent Claims (21, 22)
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23. In a microprocessor having I/O connection means, internal logic and an IEEE 1149.1 (JTAG) complaint interface including a boundary scan register (BSR), said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, the improvement comprising:
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at least one design-specific test data register adapted to receive JTAG instructions from an external controller; on-chip ROM containing a debug monitor; at least a debug state wherein said internal logic fetches instructions from a debug monitor and executes commands in said debug monitor in response to at least one test mode JTAG instruction received in said design-specific test data register; and means for switching said internal logic said debug state.
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24. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic having a logic reset condition occurring when power is applied to said microprocessor, and a JTAG boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:
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detecting when power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it; setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state; reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode; wherein said system includes a boundary scan master (BSM) operatively connected to said JTAG interface and responsive to said debugger, said JTAG interface includes a device identification (ID) register; and wherein detecting when said power is applied comprises; activating said debugger prior to applying power to said microprocessor, said debugger instructing said JTAG interface to conduct an ID register scan of said microprocessor, said debugger detecting power to said microprocessor when BSM receives valid device identification values.
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25. A method of powering-up a microprocessor in a system having an external controller with a debugger, said microprocessor comprising I/O connection means, internal logic having a logic reset condition occurring when power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR), at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said method comprising:
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detecting when power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor remains in said reset condition after having power applied to it, wherein isolating said internal logic from said I/O connection means includes loading a test mode JTAG instruction into said instruction register; setting said microprocessor to a debug state while said BSR remains in said test mode, said debugger being capable of instructing said microprocessor via said design-specific test data register to execute certain commands while said microprocessor is in said debug state; and reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode. - View Dependent Claims (26)
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27. A debugger control for controlling the power-up of a microprocessor in a system, wherein said microprocessor is interconnected to at least one system component, said microprocessor comprising I/O connection means, internal logic having a reset condition occurring when power is applied to said microprocessor and a JTAG boundary scan interface including a boundary scan register (BSR) and at least one design-specific test data register, said BSR having normal and test modes, said BSR operatively connecting said internal logic to said I/O connection means in said normal mode, said BSR operatively isolating said internal logic from said I/O connection means in said test mode, said debugger control comprising instructional means for:
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detecting if power is applied to said microprocessor; isolating said internal logic from said I/O connection means by placing said BSR in said test mode while said microprocessor is in said reset condition, wherein said instructional means for isolating said microprocessor further comprises; instructional means for initializing said I/O connection means to deactivate said microprocessor relative to said system component; setting said microprocessor to a debug state; delivering JTAG instructions to said microprocessor via said design-specific data register to execute certain commands while said microprocessor remains in said debug state; and reconnecting said internal logic with said I/O connection means by returning said BSR to said normal mode.
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Specification