Process for the production of a photovoltaic material or device, material or device thus obtained, and photocell comprising such a material or device

• US 5,935,345 A
• Filed: 01/13/1997
• Issued: 08/10/1999
• Est. Priority Date: 07/13/1994
• Status: Expired due to Fees

• Current Assignee: Centre National de La Recherche Scientifique (Etablissement Public National A Caractere Scienti
• Original Assignee: Centre National de La Recherche Scientifique (Etablissement Public National A Caractere Scienti
• Inventors: Kuznicki, Zbigniew T.
• Primary Examiner(s): CHAPMAN, MARK A
• Application Number:
  US08/765,948
• Time in Patent Office: 939 Days
• Field of Search: 136/255, 438/97, 438/488
• US Class Current: 136/255
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1864 Annealing
• CPC Class Codes: H01L 31/1872 Recrystallisation
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A process for the production of a photovoltaic material or device based on monocrystalline silicon adapted to absorb particularly infrared radiation. A wafer, a slice or a chip region of monocrystalline silicon having a diffusion length greater than the path of the minorities in the base or greater than the total thickness of the wafer, slice or chip region, is obtained. Then the rear surface of the wafer, slice or chip region, not adapted to be exposed to photovoltaic radiation, is treated so as to create a rear field as well as zones or points of electrical contact. Then the forward surface is treated so as to form a thin surface emitter layer, a P-N junction of shallow depth, as well as a continuous flat substructure strongly doped, embedded in the emitter, of very small thickness and provided with several crystalline and electrical interfaces, particularly two interfaces of the L-H type and two crystalline hetero-interfaces. Finally, the slice, wafer or chip region, particularly the surface having the emitter, is subjected to a thermal treatment, for predetermined times and temperatures, so as to obtain in the emitter layer a hetero-structure of different materials or of materials of different crystallinities, particularly a structure with at least three layers of monocrystalline silicon/amorphous silicon or modified/monocrystalline silicon type, coinciding with the doping profile adopted.

Claims

1. Process for the production of a photovoltaic material or device based on monocrystalline or polycrystalline large grain silicon, adapted to absorb particularly infrared radiation, characterized in that it consists in obtaining a wafer, a slice or a chip region of monocrystalline or polycrystalline large grain silicon having a diffusion length greater than the path of the minorities in the base or greater than the total thickness of said wafer, slice or chip region, then treating the rear surface of said wafer, slice or chip region, not adapted to be exposed to photovoltaic radiation, so as to create a rear field as well as zones or points of electrical contact, then treating the forward surface so as to form a thin surface emitter layer, a P-N junction of shallow depth, as well as at least one continuous flat substructure strongly doped, embedded in the emitter or in the base, of very small thickness and provided with several crystalline and electrical interfaces, particularly two interfaces of the L-H type and two crystalline hetero-interfaces and, finally, subjecting said slice, wafer or chip region, particularly the surface having the emitter, to a thermal treatment, for predetermined times and temperatures, so as to obtain in the emitter layer a hetero-structure of different materials or of materials of different crystallinities, particularly a structure with at least three layers of the monocrystalline silicon/amorphous silicon or modified/monocrystalline silicon type, coinciding with the doping profile adopted and comprising intrinsic fields of mechanical and electrical constraints at the level of the transition zones.

2. Process according to claim 1, characterized in that the treatment of the forward surface consists in introducing or implanting doping impurities according to a predetermined profile, having particularly an important peak of concentration of impurities coinciding with each substructure, the consecutive thermal treatment providing a determination of the geometry of each substructure, an activation of the doping impurities and of intrinsic fields localized in transition zones and a recovery of the implantation defects of doping impurities of ions in the thickness of the slice, the wafer or the chip region, with limited effect at the level of each embedded substructure.

3. Process according to claim 2, characterized in that the energy of implantation of the doping impurities used is of the order of several tens or hundreds of KeV, particularly greater than about 150 KeV, and in that the implantation dose used corresponds to an ion current of the order of several μ

A. cm^-2 or of several fractions of μ

A. cm^-2, particularly below 1 μ

A. cm^-2.

4. Process according to claim 1, characterized in that it consists, during treatment of the front surface, in providing an epitaxy or an implantation at a given depth, of an active material, particularly of Ge, followed if desired by a thermal treatment and a possible epitaxy of silicon adapted to form the superficial front surface of the emitter, as well as active generation zones by impact.

5. Process according to claim 1, characterized in that it consists in providing the slice, wafer or chip region with a rear field and having good crystalline quality, first at least an amorphized layer having optical properties permitting absorption of infrared radiation, then subjecting to a conventional epitaxial growth an emitter with at least two doping levels, the weaker on the side of the P-N junction and the higher on the side of the front surface, these two regions of different doping level being separated by at least one substructure or very thin and strongly doped embedded layer.

6. Process according to claim 1, characterized in that the treatment of the front surface consists in providing an epitaxial increase of the emitter, with a doping profile comprising particularly at least one continuous flat very strongly doped layer constituting the substructure or substructures embedded in the thickness of the emitter, then subjecting said front surface to the implantation of ions of a neutral agent such as particularly hydrogen, silicon or the like and a thermal treatment forming particularly the active zones of generation by impacts.

7. Process according to claim 6, characterized in that it consists, after implantation of ions of a neutral agent, in subjecting particularly the emitter to a thermal treatment adapted on the one hand to provide a determination of the geometry of the substructure or substructures, an activation of the doping impurities and a recovery of the implantation defects of the ions of neutral agent in the thickness of the slice, the wafer or the chip region, with limited effect in the embedded substructure or substructures and, on the other hand, to modify the crystallinity of the substructure or substructures at the level of the zones of electrical transition and constraints and the opto-electronic properties at the mesoscopic level by a repositioning of the hetero-interfaces and the L-H homo-interfaces by an effective recrystallization and rediffusion.

8. Process according to claim 1, characterized in that the thermal treatment consists in a conventional annealing, continuous or by separate stages, at a temperature equal to or less than about 500°

C., followed if desired by a rapid annealing at a temperature comprised between 500°

C. and 1200°

C., preferably about 1000°

C., of the front superficial surface zone alone, producing a planification and a final crystalline and electric formation of the interfaces of the flat substructure or substructures embedded in the emitter, leading to the formation, on the one hand, of two flat L-H homo-interfaces, gradual or abrupt, located at the level of the limits of each substructure after the operation of doping by epitaxy or implantation and, on the other hand, of two flat hetero-interfaces delimiting each substructure after the crystalline modification and the formation of the transition zones due to annealing.

9. Process according to claim 8, characterized in that the duration of conventional annealing is comprised by an interval of about 1 to 30 minutes, as a function of the desired consecutive thermal steps and of the thermal conditions of the substrate, the precise instant of stopping said thermal treatment being determined by the verification of the absorption of luminous radiation of a given wavelength or of a range of given wavelengths, particularly in the field of red and near infrared.

10. Process according to claim 8, characterized in that the L-H homo-interfaces are overlapped, two by two, with the hetero-interfaces, at the level of the limits of each substructure, said hetero-interfaces being provided during their formation with electrical properties of the L-H type.

11. Process according to claim 9, characterized in that the thermal treatment consists in a conventional annealing at a temperature less than or equal to about 500°

C., of the assembly of the slice, wafer or chip region, followed by rapid annealing at a temperature higher than or equal to 500°

C. of the superficial region of the rear surface, comprising particularly said supplemental substructure.

12. Process according to claim 8, characterized in that the L-H homo-interfaces are located within each substructure defined by the hetero-interfaces after annealing, or enclose this latter between themselves by being located on opposite sides of the latter.

13. Process according to claim 8, characterized in that, for a given substructure, one of the L-H homo-interface/hetero-interface couples is overlapping and in that the other L-H homo-interface/hetero-interface is separate or distinct.

14. Process according to claim 1, characterized in that it consists in providing, after the operation of thermal treatments, a low temperature passivation of the front surface of the slice, wafer or chip region adapted to be exposed to luminous radiation.

15. Process according to claim 1, characterized in that the starting silicon material consists in monocrystalline or polycrystalline silicon, with a concentration of doping impurities comprised between 5×

10-cm^-3 and 5×

10¹⁷ cm^-3, said material not having impurities being adapted to be activated by the implantation energy and the thermal treatment and having self-recovery properties of its crystalline structure during implantation and recovery of its crystalline structure by conventional annealing at low temperature, below 500°

C.

16. Process according to claim 1, characterized in that the emitter has a thickness less than 1 μ

m and in that the P-N junction and the L-H junction forming the rear field have a depth less than 1 μ

m.

17. Process according to claim 1, characterized in that the final thickness of the substructure or substructures present in the emitter is comprised between 20 and 100 nm, said substructure at least present being located at a distance comprised between 50 and 700 nm from the front surface of the slice, wafer or chip region and having a high selective conductivity of majority carriers thanks to its very high dopage, higher particularly than about 10¹⁹ cm^-3, preferably about 100 times greater than the dopage of the emitter.

18. Process according to claim 1, characterized in that it consists in providing a single embedded substructure in the emitter and adapted to have an effective photovoltaic conversion activity simultaneously in the UV and visible ranges and in that infrared range.

19. Process according to claim 1, characterized in that it consists in providing several substructures distributed across the thickness of the emitter, of which each is provided with two combined fields, namely a mechanical constraint field and an electrical field, by effecting successively an implantation of an active material in one wafer or slice of monocrystalline silicon, followed by an epitaxy in solid, liquid or gaseous phase.

20. Process according to claim 1, characterized in that it consists in creating at least one supplemental amorphized substructure, very strongly doped, embedded in the emitter or in the base, in particular located for example at the level of the rear surface of the base, having a limited thickness and delimited by two interfaces of the L-H type and by two crystalline hetero-interfaces or one interface of the L-H type and one crystalline hetero-interface when the supplemental substructure is located at the level of the rear surface.

21. Process according to claim 20, characterized in that it consists in providing the supplemental substructure, having an increased activity of photovoltaic conversion for infrared radiation, by creating a rear field in the wafer or slice of monocrystalline silicon doped with boron, by diffusion of aluminum for example, by operating an auto-implantation of silicon with relatively high doses, particularly greater than 10¹⁵ cm^-3 for example, to obtain amorphization of a layer, whose thickness is for example comprised between 20 and 400 nm, across the thickness of the substrate and, finally, by providing a thermal treatment of the wafer or slice, to reach a planification of the interfaces of said substructure and of the transition zones, and a maximum suppression of the activity of the divacancies.

22. Process according to claim 20, characterized in that it consists in providing the supplemental substructure, having an increased activity of photovoltaic conversion for infrared radiation, by effecting an implantation at high dosage, particularly greater than 10¹⁵ cm^-3, with a doping impurity, such as for example aluminum, forming the rear field and the hetero-interface of the L-H type and then effecting a thermal treatment to reach a planification of the interfaces and of the transition zones of said substructure, at a maximum suppression of the divacancies.

23. Process according to claim 1, characterized in that the final structure of the slice or wafer, initially doped p, is of the emitter/base/region type of rear field with respective dopings n⁺ /p/p⁺, the implanted doping impurities being selected from the group comprised by phosphorus, antimony and arsenic, particularly by the embedded substructure or substructures in the emitter.

24. Process according to claim 1, characterized in that the final structure of the slice or wafer, initially doped n, is of the emitter/base/region type of rear field with respective dopings p⁺ /n/n⁺, the doping impurities being selected from the group formed by aluminum, boron, gallium and indium.

25. Process according to claim 1, characterized in that the slice or wafer of silicon has a total thickness comprised between 120 μ

m and about 300 μ

m.

26. Process according to claim 1, characterized in that the slice or wafer of initial silicon has a thickness comprised between 3 μ

m and 120 μ

m and is counter-cemented on a rigid support, for example on a thin plate of stainless steel.

27. Process according to claim 1, characterized in that the slice, wafer or chip region has an effective confinement of minority carriers in the emitter layer located between the front surface and the substructure at least present or the substructure the least embedded and, as the case may be, between the different substructures present in the emitter, thanks to a low temperature passivation of said front surface and to the creation of a voltage barrier at the level of each substructure resulting from the insertion of the interfaces forming thus a reservoir for minority carriers of optimum thickness, as a function particularly of the initial doping, comprised between about 50 and 700 nm.

28. Process according to claim 1, characterized in that it consists in providing a supplemental treatment at least of the front surface of the slice, wafer or chip region, by superficial configuration and/or coating with a layer of a predetermined material, so as to carry out an internal or external optical confinement across the thickness of said slice, wafer or chip region, particularly for the luminous red or infrared radiation.

29. Slice or wafer of photovoltaic material obtained by means of the production process according to claim 1, consisting essentially of monocrystalline or polycrystalline silicon of large grains and comprising a layer forming an emitter at the level of its front surface or adapted to be exposed, a rear field structure at the level of its rear surface and a P-N junction across the thickness of said slice or wafer, characterized in that it comprises moreover at least one continuous substructure strongly doped with amorphized or modified silicon, embedded in the thickness of the emitter and/or in the thickness of the base and of very small thickness, said substructure having a resistivity less than that of the starting material and being delimited by crystalline and flat electric interfaces, particularly by two flat crystalline hetero-interfaces and two L-H homo-interfaces, overlapping or not with the hetero-interfaces and corresponding to the limits of the substructure after implantation of the doping impurities or other agents and before formative annealing, said at least one substructure being moreover provided, on the one hand, with opposite intrinsic electrical fields formed at the level of each L-H homo-interface favoring the extraction of the photogenerated minority carriers in said substructure and, on the other hand, of intrinsic constraint fields formed at the level of each α

-Si/c-Si hetero-interface promoting the preservation of the centers of generation by impact, said slice or wafer thus constituting a multi-interface photovoltaic device.

30. Slice or wafer according to claim 29, characterized in that it comprises a single substructure buried in the emitter and adapted to have an effective photovoltaic conversion activity simultaneously in the UV and in the visible and in the infrared ranges.

31. Slice or wafer according to claim 29, characterized in that it comprises several substructures distributed across the thickness of the emitter, of which each is provided with two combined fields, namely a field of mechanical constraint and an electrical field, at least one of said substructures having an increased or extended activity for photovoltaic conversion in the UV and visible ranges.

32. Slice or wafer according to claim 29, characterized in that it comprises at least one amorphized supplemental substructure, very strongly doped, embedded in the emitter or in the base, in particular located for example at the level of the rear surface of the base, having a limited thickness, preferably between 20 and 400 nm, and delimited by two interfaces of the L-H type and by two crystalline hetero-interfaces when said supplemental substructure is disposed in the base or emitter or by an interface of the L-H type and by a crystalline hetero-interface when said supplemental substructure is located directly at the level of the rear surface.

33. Slice or wafer according to claim 32, characterized in that the supplemental substructure is located in the base, preferably directly at the level of the rear surface, and has a high selective conductivity of majority carriers thanks to a highly elevated active dopage, particularly greater than about 10¹⁹ cm^-3, preferably about 100 times greater than that of the neighboring base zones.

34. Slice or wafer according to claim 29, characterized in that the L-H homo-interfaces overlap the hetero-interfaces, at the level of the limits of each substructure, said hetero-interfaces being provided during their formation with electrical properties of the L-H type.

35. Slice or wafer according to claim 29, characterized in that the L-H homo-interfaces are located within each substructure defined by the hetero-interfaces after annealing, or enclose this latter within themselves by being located on opposite sides of the latter.

36. Slice or wafer according to claim 29, characterized in that, for a given substructure, one of the L-H homo-interface/hetero-interface couples is overlapping and in that the other L-H homo-interface/hetero-interface couple is separate or distinct.

37. Slice or wafer according to claim 29, characterized in that the emitter has a thickness less than 1 μ

m and in that the P-N junction and the L-H junction forming the rear field have a depth less than 1 μ

m.

38. Slice or wafer according to claim 29, characterized in that the thickness of the substructure at least present in the emitter is comprised between 20 and 100 nm, said substructure being located at a distance comprised between 50 and 700 nm from the front surface of the slice, wafer or chip region and having a high selective conductivity for majority carriers thanks to its very high active dopage, higher particularly than about 10¹⁹ cm^-3, preferably about 100 times greater than that of the neighboring emitter zones.

39. Slice or wafer according to claim 29, characterized in that it comprises at least two types of substructure of which each is active in different spectral portions, namely one, located in the emitter, being active in UV and visible light and having centers of below gap generation in the emitter disposed within one or several thin substructures and the other preferably located in the base having centers of photogeneration below the gap in the base collected in at least one large substructure.

40. Slice or wafer according to claim 29, characterized in that the slice or wafer of silicon has an effective confinement of the minority carriers within the emitter layer located between the front surface and the substructure at least present in the emitter or the substructure which is the least embedded and, as the case may be, between the different substructures present in the emitter, thanks to a low temperature passivation of said front surface and to the creation of a voltage barrier at the level of each substructure resulting from the insertion of interfaces thus forming a reservoir of minority carriers of optimum thickness, as a function particularly of the initial doping, comprised between about 50 and 700 nm.

41. Slice or wafer according to claim 29, characterized in that it has a total thickness comprised between about 120 μ

m and about 300 μ

m.

42. Slice or wafer according to claim 29, characterized in that it has a thickness comprised between approximately 3 μ

m and 120 μ

m and is counter-cemented on a rigid support, for example on a thin plate of stainless steel.

43. Photovoltaic cell or photopile, characterized in that it comprises as active material a portion of a slice, a slice or a wafer of photovoltaic material according to claim 29, at least the exposed surface of said portion of slice or wafer being shaped and/or covered with a layer of a predetermined material such as to constitute an internal and/or external optical confinement, particularly for infrared radiation, across the thickness of said active material.