Personal date/time notary device

• US 5,936,149 A
• Filed: 06/02/1995
• Issued: 08/10/1999
• Est. Priority Date: 05/05/1993
• Status: Expired due to Term

• Current Assignee: Addison M. Fischer
• Original Assignee: Addison M. Fischer
• Inventors: Fischer, Addison M.
• Primary Examiner(s): RAEVIS, ROBERT R
• Application Number:
  US08/459,524
• Time in Patent Office: 1,530 Days
• Field of Search: 73/6, 73/1.43, 368/155, 368/184, 368/186, 368/202, 364/569, 364/707
• US Class Current: 73/1.43
• CPC Class Codes: G06F 21/725 operating on a secure reference time value
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/346 Cards serving only as information carrier of service
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 7/08 by coded identity card or credit card or other personal identification means without personal verification means G07F7/02
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: G07F 7/12 Card verification
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3297 involving time stamps, e.g. generation of time stamps

Abstract

A personal data/time notary device is embodied in a token device such as a "smart card". The portable notary device includes an input/output (I/O) port, which is coupled to a single integrated circuit chip. The I/O port may be coupled to a conventional smart card reading device which in turn is coupled to a PC, lap-top computer or the like. A tamper resistant secret private key storage is embodied on the chip. The private key storage is coupled to the processor which, in turn, is coupled to a permanent memory that stores the program executed by the processor. At least one clock is embodied on the card. A second clock 14 and a random value generator 10 are also preferably coupled to the processor. The device combines digital time notarization into a digital signature operation to ensure that a time stamp is always automatically present. The user does not need to be involved in any additional decision making as to whether time stamping is necessary.

Claims

1. A method for calibrating an on-chip clock device to compensate for individual deviation, comprising the steps of:

taking a first clock reading from a reference clock;

storing data related to the first clock reading;

taking a second clock reading from the reference clock;

storing data related to the second clock reading;

determining the number of on-chip clock device oscillations between the reference clock readings;

determining a calculated oscillation frequency using data related to the second and first reference clock readings to compute oscillations per unit time;

storing data related to the calculated oscillation frequency; and

adjusting the output of the on-chip clock device in accordance with said calculated oscillation frequency.

2. A method according to 1, further comprising the steps of:

determining the number of oscillations since a known clock reading; and

computing the current time using said number of oscillations, said calculated oscillation frequency and said known clock reading.

3. A method according to claim 2, wherein said step of computing includes the steps of dividing the number of oscillations by the calculated oscillation frequency to obtain an adjustment value;

and adding said adjustment value to said known clock reading.

4. A method according to claim 1, wherein said on-chip clock device is embodied within a time notary device having at least one memory and wherein the step of storing the calculated oscillation frequency includes the step of storing in said at least one memory a calibration value computed for said on-chip clock device of said time notary device.

5. A method according to claim 1, wherein the step determining a calculated oscillation frequency includes the step of using the difference between the second and first reference clock readings to compute oscillations per unit time.