Semiconductor reliability test chip

• US 5,936,260 A
• Filed: 08/21/1997
• Issued: 08/10/1999
• Est. Priority Date: 11/17/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando, Corbett, Tim J., Scholer, Raymond P.
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/916,114
• Time in Patent Office: 719 Days
• Field of Search: 257/48, 257/620, 257/203, 257/207, 257/208, 257/212, 257/211, 257/778
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/3163 Functional testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor test chip including a plurality test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Claims

1. A semiconductor test chip for simulating various conditions as a result of the manufacture, packaging, and use of said test chip, said test chip comprising:

a chip including a periphery formed by at least four sides, a plurality of contact pads located substantially adjacent a portion of the periphery of the chip, a portion of the plurality of contact pads being located in a first row and a second row located substantially behind the first row on a portion of at least one side of the chip; and

at least one line located substantially in a scribe area of the chip extending about a portion of the periphery of the chip.

2. The semiconductor test chip of claim 1, wherein the plurality of contact pads is located in at least two rows substantially adjacent the periphery of the chip on a portion of a periphery of the at least one side of the chip.

3. The semiconductor test chip of claim 1, wherein the plurality of contact pads is of at least two different geometric shapes.

4. The semiconductor test chip of claim 1, wherein at least two of the contact pads of the plurality of contact pads differ in size.

5. The semiconductor test chip of claim 1, wherein the plurality of contact pads includes contact pads having different pitches of mounting on the chip.

6. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending substantially throughout the periphery of the chip.

7. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion of the periphery of the chip, at least two lines of the plurality of lines having a width which differs from another.

8. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion of the periphery of the chip, each line of the plurality of lines having a spacing which differs from another line of the plurality of lines.

9. The semiconductor test chip of claim 1, wherein the plurality of contact pads is formed in a plurality of groups of contact pads, each group of pads extending substantially about one side of the periphery of the chip.

10. The semiconductor test chip of claim 1, wherein the plurality of contact pads is formed in a plurality of groups of contact pads extending substantially about the periphery of the chip, each individual group of contact pads being of different size than another group of contact pads of the plurality of contact pads.

11. The semiconductor test chip of claim 1, wherein the plurality of contact pads is formed in a plurality of groups of contact pads extending substantially about the portion of the periphery of the chip, each group of the plurality of groups of contacts including at least a first row of contact pads and at least a second row of contacts located adjacent the first row of contacts.

12. The semiconductor test chip of claim 1, wherein the chip further includes:

a polysilicon area located under a portion of the plurality of contact pads.

13. The semiconductor test chip of claim 1, wherein the chip further includes:

an area of polysilicon located under a portion of the plurality of contact pads, the area of polysilicon having at least two differing configurations.

14. The semiconductor test chip of claim 1, wherein the chip further includes:

a plurality of resistive type heaters located on a portion of the chip.

15. The semiconductor test chip of claim 14, wherein each resistive type heater of the plurality of heaters is independently connected to a connector pad on the chip.

16. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of transistors to measure any temperature gradient in the chip.

17. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of thin gate and thick gate transistor devices for measurement of temperature or ion contamination of the chip.

18. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of resistors for measurement of thermal performance of a portion of the chip and any package in which it is mounted.

19. The semiconductor test chip of claim 1, wherein the chip is substantially square in shape.

20. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially in a center portion of the chip.

21. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads in an array located in substantially a center portion of the chip.

22. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located in substantially a center of the chip, a portion of the plurality of flip chip test pads being connected in a daisy chain connection by conductors extending therebetween, the portion of the plurality of flip chip test pads being connected in a daisy chain being independent of other pads of the plurality of flip chip test pads.

23. A semiconductor test chip comprising:

a chip including a periphery formed by at least four sides, a plurality of contact pads located substantially adjacent a portion of the periphery of the chip, the plurality of contact pads forming a plurality of groups of contact pads extending substantially about a portion of the periphery of the chip, each group of the plurality of groups of contact pads including at least a first row of contact pads and at least a second row of contact pads located adjacent the first row of contact pads, a portion of the plurality of contact pads including active circuitry of the chip.

24. The semiconductor test chip of claim 23, wherein the plurality of contact pads is located in at least two rows substantially adjacent the periphery of the chip on a portion of a periphery of at least one side of the chip.

25. The semiconductor test chip of claim 23, wherein the plurality of contact pads is of at least two different geometric shapes.

26. The semiconductor test chip of claim 23, wherein at least two of the contact pads of the plurality of contact pads differ in size.

27. The semiconductor test chip of claim 23, wherein the plurality of contact pads includes contact pads having different pitches of mounting on the chip.

28. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

at least one line located substantially in a scribe area of the chip extending about a portion of the periphery of the chip.

29. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of lines located substantially in a scribe of the chip extending substantially throughout the periphery of the chip.

30. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of lines located substantially in a scribe area of the chip extending throughout a portion of the periphery of the chip, at least two lines of the plurality of lines having a width which differs from another line of the plurality of lines.

31. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of lines located substantially in a scribe area of the chip extending throughout a portion of the periphery of the chip, each line of the plurality of lines having a spacing which differs from another line of the plurality of lines.

32. The semiconductor test chip of claim 23, wherein the plurality of contact pads is formed in a plurality of groups of contact pads, each group of pads extending substantially about one side of the periphery of the chip.

33. The semiconductor test chip of claim 23, wherein the plurality of contact pads formed in a plurality of groups of contact pads extends substantially about the periphery of the chip, each individual group of contact pads being of a different size than another group of contact pads of the plurality of contact pads.

34. The semiconductor test chip of claim 23, wherein the chip further includes:

a polysilicon area located under at least a portion of the plurality of contact pads.

35. The semiconductor test chip of claim 23, wherein the chip further includes:

an area of polysilicon located under a portion of the plurality of contact pads, the area of polysilicon having at least two differing configurations.

36. The semiconductor test chip of claim 23, wherein the chip further includes:

a plurality of resistive type heaters located on a portion of the chip.

37. The semiconductor test chip of claim 36, wherein each resistive type heater of the plurality of heaters is independently connected to a connector pad on the chip.

38. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of transistors to measure any temperature gradient in the chip.

39. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of thin gate and thick gate transistor devices for measurement of temperature or ion contamination of the chip.

40. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of resistors for measurement of thermal performance of a portion of the chip and any package in which it is contained.

41. The semiconductor test chip of claim 23, wherein the chip is substantially square in shape.

42. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially in a center portion of the chip.

43. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of flip chip test pads in an array located in substantially the center portion of the chip.

44. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located in substantially a center of the chip, a portion of the plurality of flip chip test pads being connected in a daisy chain connection by conductors extending therebetween, the portion of the plurality of flip chip test pads being connected in the daisy chain being independent of other test pads of the plurality of flip chip test pads.